Frame Caching Apparatus for Multiprocessor SoC Memory Access
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Solution Overview
Problem
Multiprocessor SoCs with heterogeneous cores face challenges in efficiently processing large-capacity two-dimensional data due to limitations in accessing main memory, including the need for complex DMA operations, memory alignment, and double buffering, especially when dealing with non-uniform block sizes and overlapping data blocks.
Innovation Solution
A frame caching apparatus and method that allows for efficient caching and prefetching of large-capacity two-dimensional image frames by setting an initial mode based on received information, using a processing module to cache frames from the main storage unit, and providing an interface that simplifies programming by using DMA, multiple associativity, and spatially predictive prefetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DMA operations are used to access main memory from SPE local stores, then data transfer capability is improved, but operation complexity and overhead increase
Solution Approach 1:
The patent introduces a frame cache as an intermediary component between the SPE local stores and main memory. This frame cache stores frame data in a format optimized for SPE access patterns, eliminating the need for complex DMA operations while maintaining efficient data transfer capability.
Solution Approach 2:
The frame cache pre-loads and pre-processes frame data into an optimized format before SPE access is needed. By performing preliminary actions to organize data in advance, the system avoids complex runtime DMA operations and enables direct SPE access to cached frame data.
2Volume of stationary object
If frame data is stored in main memory with standard memory layout, then storage capacity is improved, but access efficiency for SPE processing deteriorates
Solution Approach 1:
The frame cache implements local quality by storing data in a location-specific format optimized for SPE access patterns. Different regions of the frame cache are organized according to how SPEs will access them, rather than using a uniform main memory layout, thereby improving access efficiency without sacrificing storage capacity.
Solution Approach 2:
The patent transforms the one-dimensional linear memory layout of main memory into a two-dimensional frame structure in the cache, organized by blocks and lines that match SPE processing patterns. This dimensional transformation enables efficient spatial access while maintaining storage capacity.
3Ease of operation
If blocks are processed in raster scan direction from main memory, then memory access simplicity is improved, but processing efficiency for non-uniform blocks deteriorates
Solution Approach 1:
The frame cache dynamically organizes blocks based on their specific processing requirements rather than enforcing a rigid raster scan order. Blocks can be arranged and accessed in various patterns depending on the processing needs, enabling both simple access and high processing efficiency for non-uniform block structures.
4Manufacturing precision
If overlapping blocks are processed separately, then processing accuracy is improved, but processing time and complexity increase
Solution Approach 1:
The frame cache merges overlapping blocks by storing them in a shared cache structure where common regions are held in a single location. This allows multiple SPEs to access the same overlapping data simultaneously without redundant transfers, maintaining processing accuracy while reducing processing time and complexity.
Data Source
AI summary
An apparatus and method of caching a frame is provided. The method of caching a frame includes receiving information on a frame to be cached from a main storage unit, setting an initial value of a specified mode using the received information, and caching the frame from the main storage unit using the specified mode.