Frame Data Reuse Across Multi-Processor Image Recognition Pipelines

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Solution Overview

Problem

Conventional processing systems experience mismatches in processing speed and data transfer speed, leading to reduced overall system performance and inability to handle complex computational processes efficiently, particularly in image processing and graphics processing.

Innovation Solution

A multi-dimensional data processing architecture that includes a system-on-chip (SoC) with multiple processors and a memory device, enabling parallelized execution and reuse of frame data across processors to accelerate image feature recognition by processing data in multiple dimensions and reducing redundant data loading operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional processing systems are used, then system simplicity is maintained, but processing speed and data transfer speed mismatch leading to reduced overall system performance

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system is divided into multiple specialized processors (first processor, second processor, third processor) each handling specific processing tasks. This segmentation allows parallel processing of different aspects of the computational workload, thereby increasing overall processing speed while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces multi-dimensional data processing capabilities where data is processed across multiple dimensions simultaneously. The first processor handles initial dimension processing, the second processor handles additional dimensions, and the third processor performs final processing. This dimensional approach enables the system to handle complex computational processes that cannot be efficiently processed by conventional single-dimension systems

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If data is processed by single processor sequentially, then device complexity is low, but processing speed and responsiveness in low-latency environments is insufficient

Engineering Contradiction:
Improvedata processing speedVSAvoidprocessor architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Multiple processors are merged into a unified system that shares common memory and coordinate through standardized interfaces. The first processor, second processor, and third processor work together as an integrated system, combining their individual processing capabilities to achieve high-speed data processing while maintaining system coherence through shared memory access

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each processor in the system is designed with multi-functional capabilities to handle different types of processing operations. The processors can perform various computational tasks including feature recognition, data transformation, and result synthesis. This universality allows the system to achieve high processing speeds across diverse computational workloads without requiring specialized hardware for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If frame data is reloaded for each processor, then data access simplicity is maintained, but redundant data loading operations reduce processing efficiency

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddata loading time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The first processor performs preliminary processing of the input frame data and stores the processed output in the shared memory device before the second processor needs it. This preliminary action ensures that data is prepared and available in advance, eliminating the need for redundant loading operations and reducing data access time for subsequent processors

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processed output from the first processor is copied to the shared memory device, creating a reusable data copy that the second processor can access without requiring the original data to be reloaded. This copying mechanism allows efficient data sharing between processors and eliminates redundant data loading operations

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20260051161A1Architecture for reuse of frame data across multi-dimensional data processors
Publication Date: 2026.02.19 NVIDIA CORP
  • US20260051161A1 patent drawing
  • US20260051161A1 patent drawing
  • US20260051161A1 patent drawing

AI summary

Aspects of this technical solution can increase speed of processing in low-latency application areas, while maintaining integrity of image feature recognition at those higher speeds. For example, in image-processing environments associated with autonomous navigation (e.g., driving), a large volume of image data is to be rapidly and accurately processed to maintain reliable and up-to-date models of a physical environment. For example, embodiments in accordance with this disclosure can provide high-speed and accurate image feature recognition of input frame data beyond the capability of CPU processing or general GPU processing to achieve.