Configurable Frame Filtering Circuit for Multi-Protocol Classification

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Solution Overview

Problem

Existing frame filtering technologies in automotive and industrial applications face challenges with complex silicon footprints, high power consumption, and inflexibility due to customised protocols, especially for high event rate communications networks like Ethernet and CAN.

Innovation Solution

A circuit comprising configurable comparator units, a crossbar switch, and result-combining logic units that allow flexible frame classification and filtering, using configurable interconnects and multiple modes to adapt to different applications, reducing resource usage and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel filter arrangements with deeper filtering are used to handle high event rates and multiple protocols, then filtering capability and speed are improved, but silicon footprint and power consumption increase significantly

Engineering Contradiction:
Improvefiltering speedVSAvoidsilicon footprint
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements a universal filter arrangement where a single pool of filters can handle multiple communication protocols (CAN, Ethernet, LIN, FlexRay) through configurable filter criteria. The filters can be programmed with different match conditions including identifier ranges, mask patterns, and protocol-specific fields, allowing one filter instance to serve multiple protocol types rather than requiring dedicated filter hardware for each protocol.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The filter arrangement employs dynamic configuration capabilities where filter criteria, match conditions, and evaluation rules can be programmatically adjusted based on the protocol being processed. The system can dynamically switch between different filtering strategies (e.g., exact match vs. range match, priority-based vs. first-come-first-served) without requiring physical reconfiguration, enabling adaptive filtering for varying event rates and protocol requirements.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If deeper forms of filtering are implemented to increase filtering capability, then filtering precision is improved, but device complexity increases

Engineering Contradiction:
Improvefiltering precisionVSAvoidfilter complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The filter criterion is segmented into multiple independent components including identifier fields, mask patterns, range specifications, and protocol-type indicators. Each component can be independently configured and evaluated, allowing the system to build complex filtering logic through combinations of simple, manageable segments rather than requiring monolithic complex filter logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes filtering parameters dynamically based on protocol type and event rate requirements. Filter match conditions can switch between exact match, range match, and pattern match modes. Priority values and evaluation rules can be adjusted as parameters to optimize filtering precision for different protocols without increasing structural complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12375426B2Frame data processing
Publication Date: 2025.07.29 RENESAS ELECTRONICS CORP
  • US12375426B2 patent drawing
  • US12375426B2 patent drawing
  • US12375426B2 patent drawing

AI summary

A circuit for use in frame filtering is disclosed. The circuit includes a plurality of comparator units. Each comparator unit configured, in response to receiving at least a part of a data frame, to perform a determination whether data in a portion of the at least part of the data frame matches respective reference data and to provide a result to a comparator unit output based on the determination. The circuit includes a crossbar switch having crossbar inputs coupled to respective comparator unit outputs and configured to provide sets of crossbar switch outputs via configurable interconnects; and a set of result-combining logic units, each result-combining logic unit coupled to a respective set of crossbar switch outputs, and configured to provide a respective logic unit output.