Frame Format Decoder for Wireless LAN Networks
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Solution Overview
Problem
Existing wireless LAN receivers face challenges in determining the frame format of received data, particularly in multi-path environments with large delay spreads, which complicates equalization and requires complex processing to handle inter-symbol and inter-chip interference, and necessitates different configurations for short and long frame formats.
Innovation Solution
A method and apparatus that count consecutive bits in the synchronization field to determine the frame format, generating a training sequence for an adaptive equalizer, allowing simultaneous determination of the frame format and training sequence, thereby simplifying the equalization process and eliminating the need for explicit SYNC field bit position detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex equalization processing is used to handle multi-path environments with large delay spreads, then receiver performance is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by detecting the frame format (short or long) before performing equalization processing. The receiver counts consecutive bits in the synchronization field to determine frame format in advance, then configures the equalizer accordingly. This preliminary detection allows the system to prepare the appropriate equalization strategy before the actual equalization occurs, reducing the complexity of real-time processing while maintaining performance in multi-path environments with large delay spreads.
2Measurement precision
If different configurations are used for short and long frame formats, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent uses preliminary action by detecting the frame format through counting consecutive bits in the synchronization field before processing the entire frame. The receiver counts bits during the synchronization field period, determines whether it's a short or long frame format, and then configures the subsequent processing accordingly. This preliminary detection simplifies the overall system by having a single detection mechanism that enables appropriate configuration selection, rather than requiring complex parallel processing paths.
Solution Approach 2:
The patent applies segmentation by dividing the frame format detection process into distinct stages: first detecting the synchronization field pattern (counting consecutive bits), then using that information to configure the rest of the receiver. The synchronization field itself is segmented into individual bits that are counted sequentially. This segmentation allows the system to handle different frame formats through a systematic, step-by-step approach rather than requiring the entire system to be reconfigurable.
3Measurement precision
If explicit SYNC field bit position detection is performed, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent applies continuity of useful action by performing the frame format detection continuously during the reception of the synchronization field itself, rather than as a separate preliminary step. The receiver counts consecutive bits as they are being received during the synchronization field period, so the detection process occurs concurrently with the natural reception flow. This eliminates additional detection time because the useful action of receiving the synchronization field simultaneously performs the frame format detection function.
Data Source
AI summary
A frame format decoder (22) and training sequence generator (24) for determining the frame format of received data which is compliant with the IEEE 802.1 1b standard for wireless local area networks, and for providing a training sequence for an adaptive equalizer (16). The received signal is first despreaded, demodulated and descrambled, so that the SYNC field is reconstructed, and then a counter 32 counts the number of consecutive bits having the same polarity or logic value until N such bits are counted (where N is an integer greater than 1). The polarity or logic value of the N counted bits enables the decoder (22) to determine whether the frame format is long or short. A training sequence, being a copy of the transmitted SYNC field eventually followed by an SFD field, is also generated for use by an adaptive equalizer (16).