Frame Gate pMOS Transistor GIDL Reduction
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Solution Overview
Problem
Conventional methods for reducing Gate-Induced-Drain-Leakage (GIDL) currents in pMOS transistors of sub-word drivers in DRAMs lead to increased parasitic resistance, deeper junctions, and short channel effects, making it difficult to scale down transistor gate length and chip size while maintaining ON current.
Innovation Solution
The semiconductor device employs a frame-shaped gate electrode layout with element isolation regions, asymmetric impurity profiles, and specific ion implantation techniques to form extension and pocket-implant regions, reducing GIDL currents while maintaining ON current and allowing for scaled-down transistor gate length and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If ion implantation is performed using conventional method to form extension region, then GIDL is reduced, but parasitic resistance increases and ON current decreases
Solution Approach 1:
The patent applies local quality by forming an extension region with a specific impurity concentration profile only in the drain area where GIDL occurs, while maintaining higher impurity concentration in the channel region to preserve ON current. This localized differentiation allows reducing GIDL without compromising overall transistor performance.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming an extension region with lower impurity concentration than the drain region, creating a gradual transition that reduces electric field intensity at the drain edge, thereby reducing GIDL while controlling parasitic resistance through precise concentration control.
2Object-generated harmful factors
If ion implantation is performed using conventional method, then extension region is formed, but junctions become deeper and short channel effects increase
Solution Approach 1:
The patent applies preliminary action by forming the extension region with controlled impurity concentration before forming the drain region, creating a pre-configured impurity profile that prevents excessive junction depth formation during subsequent processing steps, thereby maintaining precise junction depth control while reducing GIDL.
3Area of stationary object
If transistor gate length is scaled down to reduce chip size, then chip size decreases, but short channel effects increase
Solution Approach 1:
The patent applies local quality by implementing asymmetric impurity profiling with extension regions and pocket-implant regions at specific locations (drain areas) while maintaining uniform channel impurity concentration, allowing gate length scaling without exacerbating short channel effects through localized electric field management.
Solution Approach 2:
The patent transitions from one-dimensional impurity profiling to two-dimensional asymmetric profiling by adding pocket-implant regions at specific depths and locations, creating a multi-dimensional impurity distribution that controls short channel effects while enabling further gate length scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces GIDL currents, suppresses short channel effects, and enables the scaling down of chip size and transistor performance, improving the overall efficiency of pMOS transistors in sub-word drivers.
Implementation Method 1
Normally the extension region 110 is formed by ion implantation using a tilt angle (the angle at which the normal to the main surface of the semiconductor substrate 101 intersects the ion beam) of 0 degrees, and the pocket-implant region 111 is formed by ion implantation using a desired tilt angle.
Data Source
AI summary
Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.