Frame Interposer Multi-Chip Package Warpage Control

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Solution Overview

Problem

Semiconductor multi-chip packages are vulnerable to defects such as warpage due to manufacturing processes, which affects their reliability and efficiency in mass production.

Innovation Solution

A multi-chip package design incorporating a frame interposer with a first and second chip stack, covered by an encapsulant, where the frame interposer has a symmetrical structure with frame leads and pads, and the chip stacks are arranged in a cascade or overhang configuration, with external contact terminals for electrical connectivity, enhancing mechanical strength and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multi-chip package structures are used, then chip stacking is achieved, but warpage defects occur due to manufacturing processes

Engineering Contradiction:
Improvepackage reliabilityVSAvoidwarpage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by using a frame interposer structure that is asymmetric in its support distribution - the frame interposer extends along the length of the substrate and provides support primarily at the edges and corners, creating an asymmetric reinforcement pattern that counteracts the symmetric warpage forces generated during manufacturing processes

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The frame interposer serves as an intermediary element between the substrate and the chip stacks. It mediates the mechanical stresses by providing a rigid framework that distributes loads evenly, preventing direct stress concentration at the chip-substrate interfaces that would otherwise cause warpage defects

Inventive Principle:
Principle #24Intermediary (Mediator)

2Volume of moving object

If chip stacks are arranged in cascade or overhang configuration, then space utilization is improved, but mechanical strength may be compromised

Engineering Contradiction:
Improvepackage volume utilizationVSAvoidstructural strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent transitions from planar chip arrangement to three-dimensional stacking by implementing cascade and overhang configurations. Chips are arranged in multiple layers with horizontal and vertical offsets, utilizing the Z-dimension to achieve compact volume while the frame interposer provides structural support to maintain strength in this three-dimensional arrangement

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If frame interposer with openings is used, then mass production efficiency is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvemass production efficiencyVSAvoidinterposer structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The frame interposer is segmented with multiple openings that divide the structure into distinct regions. These openings allow for modular chip placement and independent processing of different interposer sections, enabling parallel manufacturing operations that improve mass production efficiency while the standardized segmentation pattern keeps the complexity manageable

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8426951B2Multi-chip package having frame interposer
Publication Date: 2013.04.23 SAMSUNG ELECTRONICS CO LTD
  • US8426951B2 patent drawing
  • US8426951B2 patent drawing
  • US8426951B2 patent drawing

AI summary

A multi-chip package is provided. The multi-chip package may include a frame interposer, a first chip stack with n number of semiconductor chips on a first surface of the frame interposer, and a second chip stack with m number of semiconductor chips on a second surface of the frame interposer. The interposer may have first and second openings. The first chip stack may extend over one of the first and second openings and may expose the other of the first and second openings. The second chip stack may extend over the other of the first and second openings and may expose the one of the first and second openings.