Frame Synchronizer Phase Control for Accurate IC Die De-Serialization
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Solution Overview
Problem
In data communication between integrated circuit (IC) dies, ensuring proper de-serialization of serial data signals received at the receiving IC die with accurate clock timing remains a challenge.
Innovation Solution
A frame decoding circuit and method that includes a frame synchronizer and de-serializer unit, which adjusts the phase of the output clock signal based on the input frame signal, using a delay-locked-loop (DLL) clock signal to de-serialize input data, ensuring correct data conversion from serial to parallel form.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted in serial form between IC dies, then data transmission speed is improved, but clock timing synchronization becomes difficult to maintain
Solution Approach 1:
The frame synchronizer performs preliminary actions by detecting frame synchronization signals before actual data processing begins. It pre-adjusts the phase of the output clock signal based on the detected frame synchronization signal, ensuring that clock timing is properly synchronized before high-speed serial data transmission starts. This preliminary phase adjustment prevents timing errors during the actual data transfer.
Solution Approach 2:
The frame synchronizer implements a feedback mechanism by continuously monitoring the incoming serial data for frame synchronization signals and using this information to dynamically adjust the phase of the output clock signal. The phase adjustment is based on feedback from the detected frame synchronization signal, creating a closed-loop system that maintains reliable clock timing synchronization even during high-speed serial transmission.
2Device complexity
If de-serialization is performed without frame synchronization, then device complexity is reduced, but data conversion accuracy deteriorates
Solution Approach 1:
The frame synchronizer performs preliminary detection of frame synchronization signals and pre-adjustment of clock phase before the actual de-serialization process begins. This preliminary action ensures that the de-serializer unit receives properly synchronized clock signals, enabling accurate data conversion without requiring complex synchronization logic within the de-serializer itself, thus maintaining data conversion accuracy while controlling overall device complexity.
3Measurement precision
If phase adjustment is performed continuously, then clock timing accuracy is improved, but energy consumption increases
Solution Approach 1:
The frame synchronizer performs phase adjustment periodically based on the detection of frame synchronization signals rather than continuously. When a frame synchronization signal is detected, the phase of the output clock signal is adjusted; otherwise, the phase remains unchanged. This periodic action maintains accurate clock timing synchronized with the incoming data while significantly reducing energy consumption compared to continuous phase adjustment.
Data Source
AI summary
A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.