Frame Synchronization via Contention Prevention and Low Power Clock
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Solution Overview
Problem
Existing power management schemes for integrated circuits are inefficient in preventing collisions during data transmission, as collision detection methods consume significant power and allow collisions to occur before rescheduling transmissions.
Innovation Solution
A device and method for frame synchronization that uses a media access controller to provide high frequency clock signals during data transmission, detect media access requests, and initiate a contention prevention period to prevent simultaneous transmissions, while maintaining the clock line in a low power mode when idle, thereby reducing power consumption and preventing collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If collision detection schemes are used to prevent simultaneous transmissions, then collision prevention is achieved, but power consumption increases significantly
Solution Approach 1:
The patent implements a contention prevention period before actual data transmission begins. During this period, the master device sends contention prevention bits to all slave devices, proactively preventing collisions before they can occur. This preliminary action eliminates the need for post-collision detection and rescheduling, thereby reducing power consumption while maintaining reliable collision-free transmission.
Solution Approach 2:
The patent introduces a master device as an intermediary that coordinates communication between slave devices. The master device manages the contention prevention period, sends control bits to slaves, and orchestrates the transmission schedule. This intermediary structure enables centralized control that prevents collisions without requiring each slave to continuously monitor and detect collisions, thus reducing overall power consumption.
2Measurement precision
If clock signals are continuously provided to maintain synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clock signaling where the master device provides clock signals only during specific transmission periods rather than continuously. The clock line transitions between active and low-power states in a periodic manner, synchronized with data transmission frames. This approach maintains synchronization accuracy during active communication while significantly reducing power consumption during idle periods.
Solution Approach 2:
The patent dynamically changes the clock signal parameter by switching between active and low-power states based on transmission needs. During data transmission, full-frequency clock signals are provided for accurate synchronization; during idle periods, the clock line enters low-power mode with reduced or no signaling. This parameter change strategy maintains synchronization precision when needed while minimizing power consumption when not needed.
Data Source
AI summary
A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.