Frame Synchronization Device Preventing Erroneous Lock in Optical Systems
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Solution Overview
Problem
In high-speed optical communication systems, such as those using SDH technology, frame synchronization is often incorrectly established due to unstable conditions like system startup or fiber disconnection, leading to prolonged recovery times and performance degradation.
Innovation Solution
A communication system that prevents synchronization establishment when a frame synchronization pattern coincides with unstable patterns like all-zero or all-one bit strings, using a frame synchronization device that compares phase-shift corrected signals and controls synchronization to avoid erroneous detection during abnormal system states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frame synchronization is established by comparing synchronization patterns in unstable conditions (system startup or fiber disconnection), then synchronization can be quickly re-established, but erroneous synchronization detection occurs due to all-zero or all-one bit patterns
Solution Approach 1:
The patent applies preliminary anti-action by detecting all-zero or all-one bit patterns before synchronization establishment and preventing synchronization in these conditions. The frame synchronization device includes a determination unit that identifies prohibited patterns and a control unit that prohibits synchronization when such patterns are detected, thereby preventing erroneous synchronization detection before it can occur during unstable system states
Solution Approach 2:
The patent changes the parameter of synchronization pattern selection by introducing prohibited patterns (all-zero and all-one bit strings) that are excluded from valid synchronization patterns. This parameter change allows the system to distinguish between valid and invalid synchronization conditions, preventing erroneous synchronization while maintaining the ability to quickly re-establish synchronization when valid patterns are detected
2Ease of operation
If the system uses a fixed frame synchronization pattern, then synchronization detection is straightforward, but the system is vulnerable to erroneous detection during abnormal states when all-zero or all-one patterns occur
Solution Approach 1:
The patent applies local quality by differentiating between valid and invalid synchronization patterns within the frame structure. By marking specific bit patterns (all-zero and all-one) as prohibited locally, the system maintains simple synchronization detection for valid patterns while introducing localized restrictions that prevent erroneous detection during abnormal states, thus improving reliability without compromising operational simplicity
Data Source
AI summary
A frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially is presented. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.