Frame Synchronizer Kick-Pin Delay for Power Reduction
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Solution Overview
Problem
Existing frame synchronization methods in digital data transmission systems, such as SDH/SONET and Gigabit Ethernet, face inefficiencies in power dissipation and synchronization speed, particularly in recognizing the frameheader or comma byte at the receiving end, which affects accurate demultiplexing and alignment of data.
Innovation Solution
A frame synchronizing device and method utilizing a serial input parallel output shift register with a 'kick-pin' control signal that delays output until frameheader detection is achieved, allowing synchronization in the parallel clock domain using low-frequency signals, thereby reducing power dissipation and ensuring accurate byte alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a resetable clock-divide-by-N counter is synchronized to the frameheader byte position at full operation speed, then synchronization speed is improved, but power dissipation increases
Solution Approach 1:
The invention uses periodic sampling of the serial bit stream at the parallel output of the shift register, checking for frameheader presence at regular intervals. This periodic action allows synchronization to be achieved at lower speeds rather than continuous full-speed operation, thereby reducing power dissipation while maintaining synchronization capability.
Solution Approach 2:
The system uses its own parallel output data to detect the frameheader and generate the kick-pin signal. The frameheader detection is performed by examining the parallel output of the shift register itself, allowing the system to self-synchronize without external intervention, reducing the need for high-speed continuous processing.
2Measurement precision
If the outputting of frames is delayed by at least one time period when frameheader is not detected, then synchronization accuracy is improved, but productivity decreases
Solution Approach 1:
The invention introduces a kick-pin control signal that generates a single-cycle delay pulse only when needed for synchronization. This temporary, short-lived intervention corrects synchronization errors without requiring continuous delays, thus maintaining high productivity while achieving accurate synchronization when required.
Solution Approach 2:
The system performs preliminary detection of the frameheader at the parallel output before final demultiplexing. By checking for the frameheader in advance and generating a kick-pin signal if absent, the system can correct synchronization issues before they affect the main data flow, ensuring accuracy without sustained productivity loss.
Data Source
AI summary
Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel output shift register means having at least as many stages as the number of bits of a frame, and said frames are outputted in a consecutive order from a parallel output portion of said shift register means. The particularity of the present invention is that it is detected whether or not a frameheader is present in the output of said parallel output portion, and, if not, the outputting of a frame from said parallel output portion is delayed by at least one time period which is needed for shifting a bit in said serial input portion from a stage to a next one, until synchronization is reached.