Frame Write Controller for Asynchronous Video Buffer Management

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Solution Overview

Problem

Conventional frame rate conversion methods face challenges with frame tear issues due to differences in input and output frame rates, leading to reduced buffer capacity and increased costs when trying to maintain frame quality.

Innovation Solution

A device and method that control frame input and output by determining whether to receive an input frame based on input and output control parameters, using a buffer, buffer control circuit, and frame write controller to generate write and read control signals, ensuring asynchronous operation to prevent frame tear.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the buffer is divided into two frame buffer areas to prevent frame tear, then frame tear problem is alleviated, but the buffer capacity for each frame is reduced

Engineering Contradiction:
Improveframe tear preventionVSAvoidbuffer capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic frame buffer management by selectively enabling or disabling frame buffer areas based on real-time input and output frame rates. The controller dynamically determines whether to use one or two frame buffer areas, adjusting the buffer configuration adaptively rather than statically, thereby optimizing both frame tear prevention and buffer capacity utilization

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (frame buffer area configuration) based on varying frame rate conditions. When input and output frame rates differ significantly, the system switches to two-frame-buffer mode to prevent frame tear; when frame rates are closer, it uses single-frame-buffer mode to maximize capacity, thus adapting to different operational states

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the buffer capacity is increased to support higher frame quality, then frame quality is improved, but the cost increases

Engineering Contradiction:
Improveframe qualityVSAvoidbuffer capacity
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent employs dynamic buffer allocation that adjusts buffer usage based on actual frame rate differences between input and output. This dynamic approach allows the system to maintain high frame quality when needed while minimizing buffer usage when frame rates are closely matched, thereby reducing the overall buffer capacity required compared to static allocation methods

Inventive Principle:
Principle #15Dynamics

3Device complexity

If the same buffer is used for both input and output operations simultaneously, then buffer usage is simplified, but frame tear occurs when frame rate difference is large

Engineering Contradiction:
Improvebuffer control complexityVSAvoidframe integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a frame buffer controller as an intermediary component that manages the interaction between input and output operations. This controller monitors frame rate differences and coordinates buffer access, preventing frame tear by controlling when simultaneous input-output operations occur, thus maintaining frame integrity without significantly increasing system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8471859B2Device and method for controlling frame input and output
Publication Date: 2013.06.25 REALTEK SEMICON CORP
  • US8471859B2 patent drawing
  • US8471859B2 patent drawing
  • US8471859B2 patent drawing

AI summary

A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.