Framebuffer Pixel Format Conversion for Compact 24-Bit Storage

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Solution Overview

Problem

Computer systems face inefficiencies in handling 24-bit pixel data due to mismatched data formats between processors and framebuffers, leading to complex memory access and potential data corruption.

Innovation Solution

A memory management unit (MMU) is introduced to convert pixel data formats between master modules and a framebuffer, adding or removing additional bits to align with the framebuffer's resolution, enabling efficient 32-bit processing while maintaining pixel integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If pixels are stored compactly one after another in the framebuffer to maximise memory occupation, then memory usage is optimized, but memory access complexity increases and pixel data may be corrupted

Engineering Contradiction:
Improvememory occupationVSAvoidmemory access complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

A memory management unit (MMU) is introduced as an intermediary component between the master module and the framebuffer. The MMU handles the complex task of reading multi-word pixels, formatting them into single 32-bit words by adding padding bytes, and managing memory access requests. This intermediary absorbs the complexity of compact pixel storage while presenting a simplified interface to master modules, allowing pixels to be stored compactly without increasing access complexity for the main system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If pixels are stored with padding to match framebuffer resolution (32 bits per pixel), then memory access is simplified, but memory occupation is reduced

Engineering Contradiction:
Improvememory access simplicityVSAvoidmemory occupation
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The system applies different storage strategies to different regions or contexts. At the framebuffer level, pixels are stored compactly (24 bits) to maximize memory occupation. At the master module interface level, pixels are presented with local padding (32 bits) to simplify access. The MMU dynamically applies the appropriate formatting based on the operation context, allowing both compact storage and simple access to coexist in different layers of the system.

Inventive Principle:
Principle #3Local quality

3Productivity

If the framebuffer uses 32-bit resolution to reduce the number of memory accesses, then access efficiency is improved, but pixel data format compatibility becomes complex

Engineering Contradiction:
Improvememory access efficiencyVSAvoidpixel format compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system changes the bit depth parameter of pixel data dynamically based on the operation type. When reading pixels for processing by master modules, the MMU converts 24-bit pixels to 32-bit format by adding padding bytes, matching the framebuffer resolution and improving access efficiency. When writing pixels to the framebuffer, the MMU converts 32-bit data from master modules back to 24-bit format, ensuring proper storage. This parameter transformation maintains compatibility across different system components while optimizing each operation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12632918B2Computer system for processing pixel data of an image
Publication Date: 2026.05.19 STMICROELECTRONICS (ROUSSET) SAS
  • US12632918B2 patent drawing
  • US12632918B2 patent drawing

AI summary

In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.