FRD Semiconductor Layer Layout for Lower Switching Loss

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Solution Overview

Problem

Fast Recovery Diodes (FRDs) used in power converters face challenges in resisting recovery currents during transitions from the on-state to the off-state, leading to increased switching loss and reduced immunity to current breakdown.

Innovation Solution

The semiconductor device incorporates a specific structure with a first and second insulating film, and a semiconductor part with carefully arranged semiconductor layers and contact regions, optimized to reduce the spatial distribution of holes and electrons, thereby minimizing discharge times and switching loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional FRD structure is used, then device simplicity is maintained, but recovery current resistance and immunity to current breakdown are insufficient

Engineering Contradiction:
Improveimmunity to current breakdownVSAvoidsemiconductor layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor part is divided into multiple doped semiconductor layers (first through fourth layers) with alternating conductivity types, creating distinct functional regions that segment the current flow path and improve recovery current resistance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different semiconductor layers are doped with different conductivity types (first or second conductivity type) and different impurity concentrations, creating local variations in electrical properties that optimize current distribution and enhance breakdown immunity

Inventive Principle:
Principle #3Local quality

2Loss of time

If contact regions are closely arranged, then device area is reduced, but spatial distribution of charge carriers increases leading to longer discharge times

Engineering Contradiction:
Improvedischarge timeVSAvoiddevice area
Core Design Contradiction:
Loss of timeVSArea of stationary object

Solution Approach 1:

Contact regions are arranged in a two-dimensional layout with specific spacing relationships, utilizing spatial distribution in multiple directions to optimize both discharge time and area efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If semiconductor layers are densely packed, then switching loss is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveswitching lossVSAvoidlayer arrangement precision
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The semiconductor layers are pre-configured with specific doping concentrations and conductivity types before final assembly, establishing optimal charge carrier distributions that reduce switching loss while simplifying subsequent manufacturing steps

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12249660B2Semiconductor device
Publication Date: 2025.03.11 KK TOSHIBA
  • US12249660B2 patent drawing
  • US12249660B2 patent drawing
  • US12249660B2 patent drawing

AI summary

A semiconductor device includes first and second insulating films and a semiconductor part. The semiconductor part is provided on the first insulating film and surrounded by the second insulating film. The semiconductor part includes first and fourth semiconductor layers of a first conductivity type, second and third semiconductor layers of a second conductivity type, and first to third contact regions provided respectively on the second to fourth semiconductor layer. The second to fourth semiconductor layers are arranged in a first direction on the first semiconductor layer. The fourth semiconductor layer is provided between the second and third semiconductor layers. The first and second contact regions being provided with first distances to the second insulating film in a second direction crossing the first direction. The first distances are less than a second distance in the second direction from the third contact region to the second insulating film.