Free-End Wirebond Interconnection for High-Density 3D Packaging

The patent introduces an intermediary substrate with through-layer vias that mediates the connection between die layers. Instead of direct wirebonding between die, the wirebonds connect to pads on the substrate, which then provide electrical connection through the substrate to subsequent die layers. This intermediary structure eliminates the geometric restrictions of direct wirebonding while maintaining connection reliability.

The patent segments the interconnection function across multiple independent elements: individual wirebonds, multiple pads on the substrate, and through-layer vias. This segmentation allows many-to-many connections between die layers, whereas soldering typically provides one-to-one or limited connections. The segmented approach enables high packaging density while maintaining connection flexibility.

The patent moves the interconnection from a two-dimensional edge connection to a three-dimensional through-layer connection. By routing connections through the substrate vertically rather than along the edge horizontally, the patent simplifies the routing topology and reduces the complexity of interconnecting multiple die layers while maintaining reliable electrical connections.

The patent merges the through-layer via formation with the existing substrate fabrication process. The vias are created during substrate manufacturing using standard semiconductor fabrication techniques, integrating the feedthrough functionality into the base substrate rather than adding it as a separate post-processing step. This combining approach enables routing flexibility without significantly increasing fabrication complexity.