Free-Floating Power Semiconductor Packaging for Wafer Stress Relief
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Solution Overview
Problem
High power semiconductor devices face challenges with inefficient heat dissipation and risk of wafer breakage due to inhomogeneous pressure and potential conductive particle generation at the junction termination, especially when using un bonded molybdenum disks with different diameters.
Innovation Solution
A power semiconductor device design featuring a first metal disk with a lateral size equal to or larger than the semiconductor wafer, providing a free floating interface to prevent wafer breakage and using a metal layer with a low melting point to enhance thermal and electrical coupling, along with a protection layer for hermetic sealing and stress reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If molybdenum disks with different diameters are used to compensate thermal expansion differences, then thermal stress is reduced, but wafer breakage risk increases due to inhomogeneous pressure
Solution Approach 1:
The patent applies different diameter molybdenum disks at different locations on the semiconductor wafer. The first molybdenum disk has a first diameter and the second molybdenum disk has a second diameter that is different from the first diameter. This local variation in disk diameter allows compensation for thermal expansion differences in different regions of the wafer, reducing thermal stress while maintaining structural integrity through the free-floating interface design.
2Reliability
If molybdenum disks are bonded to the semiconductor wafer, then thermal and electrical contact is improved, but conductive particles may be generated at the junction termination
Solution Approach 1:
The patent introduces a metal layer as an intermediary between the molybdenum disks and the semiconductor wafer. This metal layer serves as a mediator that maintains thermal and electrical contact between the disks and wafer without requiring direct bonding of the molybdenum disks to the wafer surface, thereby preventing conductive particle generation at the junction termination while still achieving reliable thermal and electrical coupling.
3Temperature
If pressure is applied to clamp the semiconductor wafer between metal disks, then thermal contact is improved, but wafer deformation may occur
Solution Approach 1:
The patent employs a free-floating interface between the molybdenum disks and the semiconductor wafer, allowing the disks to move dynamically in response to thermal expansion and pressure applied during clamping. The metal layer acts as a compliant intermediary that distributes pressure evenly, enabling the system to adapt to thermal and mechanical changes without causing wafer deformation, thus maintaining both thermal contact efficiency and wafer geometric integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design ensures efficient heat dissipation and reduces the risk of device failure by preventing wafer breakage and conductive particle generation, while maintaining low manufacturing costs and avoiding thermal stress.
Implementation Method 1
using a metal layer with a low melting point to enhance thermal and electrical coupling
Implementation Method 2
metal layer with a low melting point
Implementation Method 3
the first metal disk can slide along the first main side when laterally expanding due to heating up during operation of the power semiconductor device
Implementation Method 4
a protection layer for hermetic sealing and stress reduction
Data Source
AI summary
A power semiconductor device includes a semiconductor wafer having a junction and a junction termination laterally surrounding the junction. A protection layer covers the lateral side of the semiconductor wafer and covers the second main side at least in an area of the junction termination. A first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer. An interface between the first metal disk and the semiconductor wafer is a free floating interface. A metal layer sandwiched between the first metal disk and the semiconductor wafer.