Free Memory List Cache Bandwidth Reduction
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Solution Overview
Problem
Conventional data compression schemes in processor-based systems consume excessive memory bandwidth during maintenance of free memory list caches, which hampers system performance.
Innovation Solution
Implementing a compression circuit with multiple buffers for caching free memory lists, where pointers are refilled from system memory when the cache falls below a low threshold and emptied to system memory when it exceeds a high threshold, minimizing memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If free memory list cache is implemented to track available memory blocks, then memory allocation efficiency is improved, but memory bandwidth consumption increases due to excessive refill and empty operations
Solution Approach 1:
The free memory list cache is segmented into multiple independent buffer regions (first buffer, second buffer, etc.) that can be managed separately. This segmentation allows the system to refill only specific buffers when needed rather than managing the entire cache as a single unit, reducing unnecessary memory access operations and bandwidth consumption while maintaining allocation efficiency.
Solution Approach 2:
The cache pre-loads free memory block pointers into buffer regions before they are needed for allocation. By maintaining buffers with available pointers in advance and using threshold values to trigger refilling only when necessary, the system performs preliminary actions that reduce the frequency of memory bandwidth-consuming operations while ensuring allocation efficiency is maintained.
2Loss of energy
If multiple buffers are used in free memory list cache, then memory access operations are minimized, but device complexity increases
Solution Approach 1:
The cache is divided into multiple simple buffer regions with clear threshold-based management rules. Each buffer is managed independently with low threshold and high threshold values, creating a simple yet effective structure that reduces memory access operations without requiring complex management logic.
Solution Approach 2:
The system uses parameter changes (threshold values) to control buffer refill and empty operations. By monitoring the number of pointers in each buffer against predefined threshold parameters, the system automatically triggers refilling or emptying operations, providing a simple parameter-driven control mechanism that reduces complexity compared to more sophisticated cache management algorithms.
Data Source
AI summary
Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.