Freeze Logic Circuitry for Side Channel Attack Mitigation
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Solution Overview
Problem
Circuitry is susceptible to side channel attacks, such as Differential Power Analysis (DPA), due to power glitches in combinatorial logic, which can reveal cryptographic keys or secret information.
Innovation Solution
Implementing freeze logic with dual rail functionality, where outputs are only provided after all inputs are received, and using symmetric and balanced logic cells to equalize power consumption and reduce side-channel leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional combinatorial logic is used in cryptographic hardware, then circuit operation speed is improved, but susceptibility to side channel attacks increases due to power glitches
Solution Approach 1:
The circuit operation is divided into distinct phases: a pre-charge phase where all inputs are forced to a known state, and an evaluation phase where actual computation occurs. This segmentation ensures that power glitches during the pre-charge phase do not leak cryptographic information, while the evaluation phase produces correct results.
Solution Approach 2:
Before the actual cryptographic computation, a pre-charge phase is executed where all logic gates are prepared with known input states. This preliminary action ensures that any power consumption during this preparation phase does not reveal information about the secret inputs, as all gates are in a standardized initial state.
2Loss of time
If outputs are provided immediately upon receiving inputs, then circuit response time is improved, but power glitches can leak cryptographic information
Solution Approach 1:
The circuit operates in periodic cycles consisting of a pre-charge phase followed by an evaluation phase. During the pre-charge phase, all inputs are set to known values; during the evaluation phase, actual computation occurs. This periodic structure ensures that power consumption patterns do not leak information, as the pre-charge phase uses standardized input states.
Solution Approach 2:
The pre-charge phase serves as a preliminary action that prepares the circuit for actual computation. By forcing all inputs to known states before computation, any power glitches occurring during this preparation phase cannot leak cryptographic information, while the subsequent evaluation phase produces the correct cryptographic output.
3Adaptability or versatility
If asymmetric logic cells are used, then circuit design flexibility is improved, but power consumption varies creating side channel leakage
Solution Approach 1:
The pre-charge phase equalizes the power consumption state of all logic gates by forcing their inputs to known values. This creates an equipotential state where all gates consume similar power regardless of their specific logic function, preventing side channel attacks that rely on detecting power variations associated with different logic operations.
Data Source
AI summary
A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.