Frequency-Adaptive Voltage Divider for PLL Lock-In Time Reduction
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Solution Overview
Problem
Conventional PLL circuits face challenges in maintaining stability while reducing lock-in time, as they are prone to instability due to external noise and frequency fluctuations, leading to prolonged operating times.
Innovation Solution
A voltage divider with a variable resistance value that adjusts based on operating frequency, combined with an initial voltage generator, is integrated into the PLL circuit to control the initial voltage and reduce lock-in time, using a combination of fixed and variable resistors and a counting unit to select resistance devices based on operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the PLL circuit is designed to rapidly respond to frequency changes to reduce lock-in time, then the lock-in time is reduced, but the circuit becomes unstable due to external noise and frequency fluctuations
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor in the loop filter to an initial voltage level that corresponds to the expected operating frequency before the PLL locking process begins. This initial voltage is generated by a voltage divider circuit that is pre-configured based on the reference frequency. By providing this head-start voltage, the VCO starts closer to its target frequency, significantly reducing the lock-in time while maintaining stability through the controlled initial condition rather than abrupt changes.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the initial voltage level of the capacitor based on the reference frequency. The voltage divider circuit changes its output voltage parameter according to the detected reference frequency, and this adjusted initial voltage is applied to the VCO. This parameter adaptation allows the PLL to quickly adapt to different operating frequencies while maintaining stable locking, as the initial voltage matches the expected operating point.
2Device complexity
If a fixed initial voltage is applied to the VCO, then the circuit structure is simple, but the lock-in time increases when operating frequency varies
Solution Approach 1:
The patent applies dynamics by transforming the static fixed initial voltage into a dynamic voltage that automatically adapts to the reference frequency. The voltage divider circuit, controlled by the reference frequency signal, dynamically adjusts the initial voltage level applied to the capacitor. This dynamic adjustment mechanism allows the circuit to maintain optimal performance across varying operating frequencies without requiring complex external control systems, achieving frequency-adaptive lock-in time reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution maintains stability and significantly reduces lock-in time in PLL circuits, allowing them to adapt to varying operating frequencies and external conditions, thereby improving overall system performance.
Implementation Method 1
a voltage divider for dividing an input voltage to an initial control voltage of the VCO; and an initial voltage generator for generating an initial voltage having a level that varies according to an operating frequency of the semiconductor memory device in an enable section of a pulse signal
Implementation Method 2
The variable resistor has a variable resistance value that varies corresponding to a variation of the operating frequency
Data Source
AI summary
A voltage divider for dividing an input voltage includes a fixed resistor, a variable resistor, an input node and an output node. The fixed resistor has a fixed resistance value independent of an operating frequency, and includes at least one resistance device. The variable resistor has a variable resistance value that varies corresponding to a variation of the operating frequency. The input node receives the input voltage, and the output node outputs an output voltage, which includes the input voltage divided based on the fixed resistance value and the variable resistance value.