Frequency-Agile Clock Multiplier for Fast Re-Lock Across Input Changes
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Solution Overview
Problem
Conventional phase-locked loop (PLL) multipliers incur significant latency during frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility due to their narrow input frequency range, hindering efficient power conservation in frequency-agile systems.
Innovation Solution
A frequency-agile, fast-locking clock multiplier unit that compares a variable-frequency input clock with a self-generated reference clock to rapidly lock the output clock to a frequency multiple, utilizing a wide-range oscillator with spectrally staggered component oscillators and a fast frequency comparator to achieve low-latency frequency transitions across a broad range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase-locked loop (PLL) multipliers are used, then a broad input frequency range is achieved, but significant latency is incurred during frequency changes
Solution Approach 1:
The oscillator is divided into multiple component oscillators (first, second, third, and fourth oscillators) with spectrally staggered lock ranges. This segmentation allows the system to cover a broad input frequency range while each individual oscillator maintains a narrow, optimized lock range for fast locking.
Solution Approach 2:
The system dynamically selects which component oscillator to use based on the input clock frequency. The spectrally staggered lock ranges are adjusted to overlap, enabling seamless transitions between oscillators as frequency changes, achieving both broad range coverage and fast lock times.
2Loss of time
If injection-locked oscillators are used, then fast lock times are achieved, but a narrow input frequency range is incurred
Solution Approach 1:
The oscillator is divided into multiple component oscillators (first, second, third, and fourth oscillators) with spectrally staggered lock ranges. This segmentation allows the system to cover a broad input frequency range while each individual oscillator maintains a narrow, optimized lock range for fast locking.
Solution Approach 2:
The clock multiplier unit serves multiple functions: it operates as an injection-locked oscillator for fast locking, while the spectrally staggered component oscillators collectively provide broad frequency range coverage, combining the advantages of both approaches.
3Use of energy by moving object
If frequency scaling is performed to conserve power, then power consumption is reduced, but latency is incurred during frequency transitions
Solution Approach 1:
The system dynamically selects which component oscillator to use based on the input clock frequency. The spectrally staggered lock ranges are adjusted to overlap, enabling seamless transitions between oscillators as frequency changes, achieving both broad range coverage and fast lock times.
Solution Approach 2:
The frequency comparator continuously monitors the input clock frequency and provides feedback to select the appropriate component oscillator. This feedback mechanism ensures that the system can rapidly respond to frequency changes and maintain optimal power consumption without significant latency.
Data Source
AI summary
A clock generating circuit is operated in a phase-locking mode to generate an output clock signal having a first frequency that is phased-locked with respect to a variable-frequency input clock signal. After a frequency transition in the input clock signal, phase-locking is disabled within the clock generating circuit to transition the output clock signal from the first frequency to a second frequency that lacks phase-alignment with the input clock signal, then a frequency-lock range of the clock generating circuit is adjusted to transition the output clock signal from the second frequency to a third frequency that also lacks phase alignment with the input clock signal. After adjusting the frequency-lock range of the clock generating circuit, phase-locking is re-enabled therein to transition the output clock signal from the third frequency to a fourth frequency that is phase-aligned with the variable-frequency input clock signal.