Frequency-Agile Clock Multiplier with Open-Loop Re-Lock Control
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Solution Overview
Problem
Conventional phase-locked loop (PLL) multipliers incur significant latency during frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility due to their narrow input frequency range, hindering efficient power conservation in frequency-agile systems.
Innovation Solution
A frequency-agile, fast-locking clock multiplier unit that compares a variable-frequency input clock with a self-generated reference clock to rapidly lock a wide-range oscillator to a frequency multiple of the input clock, utilizing spectrally staggered component oscillators and tunable MILOs to achieve low-latency frequency multiplication across a broad range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLL multipliers are used, then broad input frequency range is achieved, but long re-lock time and latency are incurred
Solution Approach 1:
The patent segments the frequency multiplication function into multiple parallel paths: a main PLL path for broad frequency coverage and a bypass path with injection-locked oscillators for fast locking. The system selectively activates appropriate paths based on frequency transition requirements, thereby resolving the contradiction between broad input range and fast re-lock time.
Solution Approach 2:
The patent implements preliminary frequency prediction and pre-positioning of oscillator states. Before a frequency transition occurs, the system predicts the target frequency and pre-configures the oscillator pathways, enabling faster lock acquisition without sacrificing broad frequency adaptability.
2Loss of time
If injection-locked oscillators are used, then fast lock time is achieved, but narrow input frequency range limits frequency agility
Solution Approach 1:
The patent merges injection-locked oscillators with PLL-based frequency synthesizers in a hybrid architecture. The injection-locked oscillators provide fast locking for frequent frequency transitions, while the PLL maintains broad frequency coverage. This combination resolves the contradiction by integrating the strengths of both approaches.
Solution Approach 2:
The patent implements dynamic switching between different frequency multiplication pathways based on real-time system requirements. The system dynamically selects between injection-locked paths (for fast locking) and PLL paths (for broad frequency range), thereby achieving both fast lock time and wide frequency agility through adaptive configuration.
3Use of energy by moving object
If frequency switching is performed to conserve power, then power consumption is reduced, but latency during frequency transitions increases
Solution Approach 1:
The patent introduces an intermediary frequency prediction and control mechanism that mediates between power management requirements and performance requirements. The system predicts upcoming frequency transitions and pre-configures oscillators accordingly, reducing the actual transition latency while maintaining the power-saving benefits of frequency scaling.
Solution Approach 2:
The patent performs preliminary frequency prediction and oscillator pre-positioning before actual frequency transitions occur. This advance preparation minimizes the effective latency experienced during frequency changes, allowing the system to switch frequencies for power conservation without incurring significant performance penalties.
Data Source
AI summary
A clock generating circuit is operated in a closed-loop state to generate an output clock signal that is frequency-locked with respect to an oscillatory input signal. Upon detecting a frequency transition in the input signal, the clock generating circuit is switched from the closed-loop operating state to an open-loop operating state to enable the output clock signal to oscillate at a free-running frequency. A ratio between input signal frequency and the free-running frequency of the output clock signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output clock signal with respect to input signal.