Frequency Conversion Unit for High-Speed Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed semiconductor memory devices require expensive test devices capable of generating high-speed clock signals, creating a demand for cost-effective methods using low-speed testers.
Innovation Solution
A semiconductor test device comprising a low-speed tester, a reference clock generating unit, a control unit, a clock converting unit, and a test data converting unit that convert low-frequency signals to high-frequency signals with reduced jitter, enabling efficient testing of high-speed semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a low-speed tester is used to test high-speed semiconductor memory devices, then the testing cost is reduced, but the clock signal frequency is insufficient for high-speed devices
Solution Approach 1:
The patent applies parameter changes by converting the frequency parameter of the clock signal from low-speed to high-speed ranges. The frequency conversion unit transforms the low-frequency clock signal from the tester into a high-frequency clock signal suitable for testing high-speed semiconductor memory devices, thereby resolving the contradiction between using low-cost low-speed testers and meeting the high-frequency requirements of modern memory devices
Solution Approach 2:
The frequency conversion unit serves as an intermediary component between the low-speed tester and the high-speed semiconductor memory device under test. This intermediary device bridges the frequency gap by converting clock signals, enabling the low-speed tester to effectively test high-speed devices without requiring an expensive high-speed tester
2Ease of manufacture
If a low-speed tester is used, then the testing cost is reduced, but the jitter of clock signals increases
Solution Approach 1:
The frequency conversion unit not only changes the frequency parameter but also improves the temporal characteristics of the clock signal. By regenerating the clock signal at the desired frequency, the system reduces jitter and improves signal integrity, thereby maintaining reliability while using cost-effective low-speed testers
Solution Approach 2:
The control unit generates control signals based on the reference clock signal and coordinates the frequency conversion process. This control mechanism ensures that the frequency conversion maintains signal integrity and minimizes jitter, providing a reliable clock signal for testing while keeping costs low
3Speed
If clock signal frequency is increased for high-speed testing, then testing capability for high-speed devices is improved, but the tester cost increases
Solution Approach 1:
The patent segments the frequency conversion function from the main tester unit into a separate frequency conversion unit. This segmentation allows the use of a low-cost base tester with an added frequency conversion module, rather than requiring an entirely expensive high-speed tester, thereby reducing overall system cost while maintaining high-speed testing capability
Solution Approach 2:
The frequency conversion unit acts as an intermediary that enables high-speed testing without requiring the entire tester system to be high-speed. This intermediary approach allows cost-effective low-speed testers to achieve high-speed testing capability through signal conversion
Data Source
AI summary
A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock signal and converting the frequency of the reference clock signal to a second clock signal in response to the control signal, and a test data converting unit receiving the first test data, converting the first test data to second test data synchronously with the second clock signal and providing the second test data to a semiconductor memory device under test.