Frequency Corrector Using Segmented Counter and Dynamic Timing
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Solution Overview
Problem
Conventional frequency correctors for clock signals, particularly those using a variable frequency divider circuit, face issues with accuracy and power consumption, leading to incomplete frequency correction and increased circuit complexity, which limits their use in portable devices.
Innovation Solution
A frequency corrector with a counter that divides the clock signal into a fraction of a natural number greater than unity, a frequency divider circuit that outputs multiple clock frequencies, and a correction timing generator that detects correction timing signals to provide accurate unit time signals, reducing circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a variable frequency divider circuit is used to correct clock frequency, then frequency correction capability is provided, but circuit complexity increases and power consumption rises
Solution Approach 1:
The patent segments the frequency correction function into two parts: a fixed frequency divider circuit that provides stable division ratios, and a separate correction mechanism that adds or subtracts clock pulses at specific timing. This segmentation avoids the need for a complex variable frequency divider while achieving frequency correction capability.
Solution Approach 2:
The patent introduces a correction pulse generator as an intermediary component that generates correction pulses to be added or subtracted from the divided clock signal. This mediator approach allows frequency correction without modifying the main frequency divider circuit, reducing overall circuit complexity.
2Use of energy by stationary object
If frequency correction is performed at an interval of 60 seconds, then power consumption is reduced, but clocking accuracy for short-duration operations deteriorates
Solution Approach 1:
The patent implements dynamic correction timing that adapts to different operational modes. For stopwatch operations, correction timing is optimized to occur at intervals suitable for short-duration measurements, while for clock operations, correction occurs at longer intervals to minimize power consumption. This dynamic adjustment resolves the contradiction between power consumption and accuracy for different applications.
Solution Approach 2:
The patent changes the correction interval parameter based on the operational mode (clock mode vs. stopwatch mode). In stopwatch mode, correction occurs at shorter intervals to maintain accuracy, while in clock mode, correction occurs at 60-second intervals to reduce power consumption. This parameter adaptation allows the system to optimize for different use cases.
3Device complexity
If a fixed frequency divider circuit is used, then circuit complexity is reduced, but adaptability to different frequency correction needs is limited
Solution Approach 1:
The patent creates a universal frequency correction mechanism that can handle both positive and negative correction values, as well as different correction intervals, using the same fixed frequency divider circuit. The correction pulse generator can generate pulses at different rates and in different directions, providing multi-functionality without increasing circuit complexity.
Solution Approach 2:
The patent uses periodic correction pulses generated at different intervals to achieve adaptability. By controlling the period and frequency of correction pulses, the system can adapt to different frequency correction needs while maintaining a simple fixed frequency divider circuit. The periodic action allows the same circuit to serve multiple correction scenarios.
Data Source
AI summary
In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.