Frequency Counter Circuit for DCO Timing Violation Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase-locked loops face challenges in compensating for digitally-controlled oscillator (DCO) gain variations due to process, voltage, and temperature (PVT) variations, leading to errors in frequency and phase output signals.
Innovation Solution
The implementation of a method for DCO gain normalization, which involves determining a run-time scaling factor to map loop filter gain constants to a nominal DCO gain, using calibration circuitry to identify the DCO operating point and calculate the scaling factor, and applying it to the loop filter coefficients to minimize gain variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DCO circuits are used without gain normalization, then the circuit complexity is lower, but DCO gain variations occur under PVT conditions leading to frequency and phase errors
Solution Approach 1:
The patent performs preliminary calibration to determine the DCO operating point and calculate run-time scaling factors before normal operation. This preliminary action stores calibration data that compensates for PVT variations, enabling accurate frequency generation without complex real-time adjustment circuits.
Solution Approach 2:
The patent introduces an intermediary calibration system that measures DCO gain variations and provides correction factors. This intermediary layer between the DCO and loop filter enables gain normalization through scaling factors, reducing frequency errors without requiring fundamental changes to the DCO structure.
2Productivity
If DCO gain normalization is implemented, then frequency accuracy improves, but the locking time decreases significantly to less than 30 reference clock cycles
Solution Approach 1:
The calibration process performs preliminary determination of the DCO operating point and pre-calculates run-time scaling factors before the PLL enters locking mode. This preliminary preparation eliminates the need for time-consuming frequency searches during locking, enabling acquisition in less than 30 reference clock cycles.
Solution Approach 2:
The patent implements feedback mechanisms that use the pre-determined operating point and scaling factors to rapidly adjust the DCO frequency. The loop filter applies normalized gain constants that provide immediate correction, accelerating the locking process while maintaining accuracy.
3Measurement precision
If frequency search algorithms are used without timing violation detection, then the search process is simpler, but timing violations may occur causing incorrect frequency measurements
Solution Approach 1:
The patent introduces an intermediary timing violation detection mechanism that monitors counter operations during frequency searches. This intermediary layer detects potential timing violations before they corrupt measurements, providing validation without requiring complete redesign of the counter circuitry.
Solution Approach 2:
The patent replaces complex mechanical timing validation methods with digital detection logic that monitors counter overflow conditions and timing signals. This substitution uses software/digital logic instead of complex hardware timing mechanisms, reducing overall system complexity while improving measurement reliability.
Data Source
AI summary
A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.