Multi-Modulus Frequency Divider Staging for Critical Path Timing
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Solution Overview
Problem
Prior multi-modulus frequency divider circuits have high delay along their critical paths, leading to erroneous generation of output clock signals and erroneous data sampling in synchronous digital circuits due to a smaller margin for error in critical stage timing.
Innovation Solution
A multi-modulus frequency divider circuit is designed with first and second frequency division stages, each comprising a modulus generation circuit and a flip-flop, which divides the input clock signal by a set of division ratios, reducing the total critical time and ensuring accurate clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior multi-modulus frequency divider circuits are used, then frequency division functionality is provided, but high delay along critical paths causes erroneous output clock signal generation
Solution Approach 1:
The frequency divider circuit is divided into multiple independent stages (first frequency division stage and second frequency division stage), each handling a portion of the overall division ratio. This segmentation reduces the critical path delay within each stage compared to a single monolithic divider, as the delay is distributed across multiple smaller units rather than concentrated in one long critical path.
Solution Approach 2:
The circuit employs dynamic modulus selection where the division ratio can be changed between stages based on control signals. The first stage can operate with different modulus values (N1) and the second stage with different modulus values (N2), allowing the circuit to dynamically adapt to different frequency division requirements while maintaining optimized timing characteristics for each configuration.
2Productivity
If high frequency clock signals are used, then productivity of the circuit is improved, but the margin for error in critical stage timing becomes smaller leading to erroneous sampling
Solution Approach 1:
By segmenting the frequency division into multiple stages operating at different effective frequencies, the circuit can handle high input frequencies without requiring the entire critical path to operate at the full input clock frequency. Each stage operates at a reduced frequency relative to the input, providing larger timing margins for setup and hold requirements while still achieving the overall high-frequency division function.
Solution Approach 2:
The first frequency division stage acts as an intermediary that converts the high-frequency input clock signal into a lower-frequency intermediate clock signal. This intermediate signal then serves as the clock for the second stage, effectively mediating between the high-frequency input and the lower-frequency output, thereby providing timing margins in the critical paths while maintaining high overall productivity.
Data Source
AI summary
A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.