Shared-Path Frequency Divider for Clock Delay Matching
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Solution Overview
Problem
Frequency dividers introduce propagation delay mismatch between common and reduced frequency clock signals, leading to operational issues and high power consumption due to the need for additional circuitry and power-intensive delay matching.
Innovation Solution
A frequency divider design that uses shared circuits to provide both common and reduced frequency clock signals with substantially the same propagation delay, eliminating the need for separate delay matching and reducing power consumption by integrating enable circuits and output circuits to function as a multiplexer without additional propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider uses separate propagation paths for common and reduced frequency clock signals, then it can provide frequency division functionality, but it introduces propagation delay mismatch between the two clock signals
Solution Approach 1:
The patent merges the propagation paths by having both the common frequency clock signal and reduced frequency clock signal traverse through the same frequency divider circuitry. This ensures that both signals experience identical propagation delays, eliminating the delay mismatch problem that would occur with separate paths.
Solution Approach 2:
The frequency divider circuit is designed to serve multiple functions: it can operate as a direct pass-through for common frequency clock signals and simultaneously perform frequency division for reduced frequency clock signals. This multi-functionality allows both signals to share the same propagation path while maintaining different operational characteristics.
2Reliability
If a model delay element is added to match propagation delays, then delay matching accuracy improves, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for separate model delay elements by redesigning the frequency divider architecture. Instead of adding delay matching components, the solution removes the fundamental cause of delay mismatch by using shared propagation paths, thereby reducing device complexity while maintaining delay matching.
3Adaptability or versatility
If a multiplexer is used to select between common and reduced frequency clock signals, then frequency selection capability is achieved, but power consumption and propagation delay increase
Solution Approach 1:
The patent merges the frequency selection functionality into the existing frequency divider circuit by using the same circuitry to both divide frequency and select between output modes. This eliminates the need for a separate multiplexer, reducing power consumption while maintaining the ability to select between common and reduced frequency clock signals.
Data Source
AI summary
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.