Frequency Divider Circuit for 50:50 Duty Ratio Mode Switching
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Solution Overview
Problem
Conventional frequency dividers require additional duty cycle correctors to achieve a 50:50 duty ratio, leading to complex structures and high power consumption, especially when switching between odd and even number frequency division modes.
Innovation Solution
A frequency divider design that includes first and second edge detection units, a pulse triggered buffer unit, and a mode selection unit, allowing for selectable odd or even number division ratios without an additional duty cycle corrector, and maintaining a 50:50 duty ratio in both modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional frequency dividers use additional duty cycle correctors to achieve 50:50 duty ratio, then the duty ratio precision is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent removes the duty cycle corrector component from the frequency divider system. By redesigning the edge detection units and mode selection mechanism, the system achieves 50:50 duty ratio without requiring the separate correction circuitry that conventional designs depend on.
Solution Approach 2:
The edge detection units are designed to perform multiple functions: they detect edges, generate count signals, and inherently produce the 50:50 duty ratio output. The mode selection unit enables the same hardware to handle both odd and even division ratios without requiring different circuit configurations or additional correction components.
2Manufacturing precision
If conventional frequency dividers use additional duty cycle correctors, then the duty ratio precision is improved, but the power consumption increases
Solution Approach 1:
The duty cycle corrector is completely removed from the system. The patent achieves 50:50 duty ratio through the inherent operation of the redesigned edge detection units and mode selection mechanism, eliminating the power consumption associated with separate correction circuitry.
Solution Approach 2:
The edge detection units self-adjust to produce the correct 50:50 duty ratio output without requiring external correction components. The system inherently manages its own duty cycle requirements through the coordinated operation of the edge detection units and mode selection unit.
3Adaptability or versatility
If frequency divider switches between odd and even number division modes, then the adaptability is improved, but the structure complexity increases due to mode switching requirements
Solution Approach 1:
The same edge detection units and buffer circuitry handle both odd and even division modes without requiring separate hardware paths. The mode selection unit configures the existing components to achieve different division ratios, allowing one set of components to serve multiple functions.
Solution Approach 2:
The frequency divider uses dynamic mode switching through the mode selection unit, which reconfigures the operation of the edge detection units based on whether odd or even division is required. This dynamic reconfiguration allows adaptability without duplicating hardware for each mode.
4Adaptability or versatility
If frequency divider achieves selectable odd or even number division ratios, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The edge detection units are designed to generate appropriate count signals for both odd and even division ratios using the same hardware structure. The mode selection unit enables this universal behavior by configuring how the edge detection units process input signals and generate output pulses.
Data Source
AI summary
A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.