Frequency Divider Latch Topology for Low-Power Multi-Phase Clocks
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Solution Overview
Problem
Conventional serializer/deserializer circuits face challenges in achieving high-speed operation with accurate timing control, leading to increased power consumption due to repeated data conversion and inversion processes, especially when dealing with large bit widths.
Innovation Solution
A frequency dividing circuit is designed with a series loop of latch circuits driven at both rising and falling clock signal phases, generating frequency divided clock signals with different phases through exclusive logical sum operations, reducing power consumption and data conversion repetitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional frequency division is performed by repeated data conversion and inversion processes, then frequency divided clock signals can be generated, but power consumption increases due to repeated data conversion and inversion
Solution Approach 1:
The patent inverts the conventional approach by using latch circuits that are driven by both rising and falling clock phases simultaneously, rather than converting data repeatedly through multiple stages. This inversion of the data conversion process eliminates redundant inversion operations and reduces power consumption while maintaining accurate timing control for frequency divided clock signal generation
2Quantity of substance
If the number of wiring is increased to enlarge bit width in parallel data transmission, then communication amount increases, but device complexity and wiring limits are reached
Solution Approach 1:
The patent transitions from parallel data transmission (increasing bit width) to serial data transmission (increasing clock frequency) by implementing efficient frequency division circuits. This dimensional change from parallel to serial architecture enables increased communication throughput without proportionally increasing wiring complexity, as the frequency divided clock signals enable higher-speed serial communication
3Measurement precision
If timing accuracy is improved in high-speed operation, then data transmission reliability increases, but power consumption increases due to more frequent clock cycles
Solution Approach 1:
The patent implements periodic action by using latch circuits that are alternately driven by rising and falling clock phases in a regular cycle. This periodic operation pattern ensures accurate timing control for frequency division while managing power consumption through the systematic alternation of active latch circuits, allowing high-speed operation with controlled energy usage
Data Source
AI summary
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.