Frequency Divider Phase Selection for Stable Clock Alignment
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Solution Overview
Problem
Frequency divider circuits face uncertainty in phase relationship between output clock signals due to noise-induced instability, leading to potential phase changes between frequency-divided clock signals, which can result in undesired phase relationships.
Innovation Solution
A frequency divider circuit comprising a first and second frequency dividing circuit, a detection circuit to monitor phase relationships, and a selection circuit to choose between the second frequency-divided clock signal and its inverted signal, ensuring the output clock signals maintain the desired phase relationship with the input clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a frequency divider circuit uses D latch circuits to divide clock signals, then the circuit structure is simple and easy to manufacture, but the phase relationship between frequency-divided clock signals becomes uncertain and unstable due to noise
Solution Approach 1:
The patent introduces a phase detection mechanism that continuously monitors the phase relationship between frequency-divided clock signals and provides feedback control. When phase deviation is detected due to noise or instability, the system adjusts the phase of the frequency-divided clock signals to maintain the desired phase relationship, thereby resolving the reliability issue while keeping the base D latch structure simple
Solution Approach 2:
The patent implements dynamic phase adjustment capability in the frequency divider circuit. Instead of a fixed phase relationship, the circuit can dynamically change the phase of output clock signals based on detected instability or noise conditions, allowing the system to adapt and maintain reliable operation under varying conditions
2Ease of operation
If the phase relationship between frequency-divided clock signals is determined by reset logic, then the circuit operation is simple, but the phase relationship changes when clock signals become unstable due to noise
Solution Approach 1:
The patent replaces static reset logic with a dynamic feedback-based phase control mechanism. The system continuously detects the phase relationship between clock signals and adjusts phases in real-time, ensuring consistent phase relationships even when input clock signals become unstable due to noise or other disturbances
Solution Approach 2:
The frequency divider circuit incorporates self-correction capability through automatic phase detection and adjustment. When phase deviation is detected, the system automatically corrects the phase relationship without external intervention, maintaining reliable operation while keeping the control mechanism integrated within the circuit itself
Data Source
AI summary
A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.