Frequency Divider Synchronization for Smooth Ratio Changes
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Solution Overview
Problem
Conventional synchronization systems face issues with timing closure due to clock skew between devices, require a large number of pins for connection, and have stringent timing requirements when changing the division ratio of the divided clock.
Innovation Solution
A synchronization system with a frequency divider circuit that includes a division ratio detection circuit to output the division ratio of the divided clock, reducing the need for additional signals and pins, and allows for smooth changes in the division ratio without timing violations by using a division ratio changing circuit to stepwisely adjust the division ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the frequency divider circuit is mounted as a separate semiconductor chip, then the first device and second device can operate in synchronization with different clocks, but the number of pins required for connection increases
Solution Approach 1:
The patent combines the frequency divider circuit with either the first device or second device into a single semiconductor chip, eliminating the need for multiple external connection pins. This integration merges previously separate functional blocks, reducing pin count while maintaining the ability to generate synchronized clocks for both devices.
Solution Approach 2:
The integrated frequency divider circuit is designed to provide clock signals to both the first device and second device simultaneously, making it a multi-functional component. This universal clock generation capability replaces what would otherwise require separate clock circuits and multiple connection pins.
2Productivity
If the division ratio is changed abruptly, then the division ratio can be updated quickly, but timing violations occur due to clock skew
Solution Approach 1:
The patent implements dynamic adjustment of the division ratio through a control signal that allows the frequency divider circuit to adapt its division ratio in real-time. This dynamic capability enables the system to respond to changing synchronization requirements while maintaining timing integrity through controlled transition mechanisms.
Solution Approach 2:
The system performs preliminary actions by pre-calculating and preparing division ratio changes to ensure timing closure is maintained. The control signal mechanism allows the system to anticipate timing requirements and adjust the division ratio in a manner that prevents timing violations before they occur.
Data Source
AI summary
In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal.