Frequency Division Correction Circuit for Uniform Four-Phase Clocks
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Solution Overview
Problem
Existing frequency division circuits struggle to generate four-phase clock signals with uniform phase differences using decimal frequency dividers, resulting in skew errors and inability to produce clock signals with desired duty ratios.
Innovation Solution
A frequency division correction circuit comprising a first frequency divider for decimal frequency division and a corrector that generates output signals with intermediate duty ratios, utilizing a duty cycle corrector to adjust the duty ratios of signals from a divide-by-1.5 divider and a divide-by-2 divider to produce four-phase clock signals with uniform phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decimal frequency division is performed using conventional frequency dividing circuits, then frequency division output can be obtained, but the duty ratio cannot be corrected and phase skew errors occur
Solution Approach 1:
The patent introduces a duty ratio correction circuit as an intermediary component between the decimal frequency divider and the output stage. This correction circuit receives the frequency division output signal and actively adjusts its duty ratio to achieve uniform 50% duty cycle, thereby resolving the duty ratio non-uniformity problem without affecting the frequency division accuracy
Solution Approach 2:
The patent changes the duty ratio parameter of the frequency division output signal through the correction circuit. By dynamically adjusting the duty ratio parameter while maintaining the frequency division ratio, the system achieves both accurate frequency division and uniform duty ratio output
2Productivity
If four-phase clock signals are generated using conventional methods, then clock signals can be produced, but uniform phase differences cannot be achieved due to skew errors
Solution Approach 1:
The patent applies parameter changes to the phase characteristics of clock signals by using the corrected duty ratio signals as inputs to phase generation circuits. This ensures that the generated four-phase clock signals have uniform 90-degree phase differences, eliminating skew errors while maintaining high productivity in clock signal generation
3Adaptability or versatility
If frequency division ratio is set to decimal numbers, then flexible frequency control is achieved, but duty ratio correction becomes difficult
Solution Approach 1:
The patent designs a universal duty ratio correction circuit that can handle various decimal frequency division ratios (e.g., 1.5, 2.5, 3.5) with a single circuit architecture. This multi-functional correction circuit simplifies the overall device complexity while maintaining flexible frequency control capability across different division ratios
Data Source
AI summary
A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.