Frequency Doubler Calibration for 50% Duty Cycle Clocks
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Solution Overview
Problem
Designing frequency generation systems for portable RF devices that meet performance requirements for clock signals while balancing cost, board space, and power consumption is challenging, particularly due to issues with duty cycle errors in clock signals affecting sensitive circuitry like ADCs and PLLs.
Innovation Solution
An adjustable frequency doubling circuit that receives a first clock signal, generates a second clock signal with a doubled frequency, and adjusts its duty cycle based on measured parameters using a duty cycle measurement and adjustment circuit, ensuring the duty cycle is substantially 50% to minimize spurious behavior and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency multiplication circuits (PLL, DLL) are used to generate high frequency clocks, then clock frequency requirements are met, but circuit complexity and power consumption increase
Solution Approach 1:
The patent combines frequency doubling functionality with duty cycle correction into a single integrated circuit block. The frequency doubler receives a first clock signal and generates a second clock signal with twice the frequency, while simultaneously correcting duty cycle errors through embedded correction logic that adjusts the output duty cycle to be substantially 50%, eliminating the need for separate correction circuits.
Solution Approach 2:
The frequency doubling circuit is designed to perform multiple functions: frequency multiplication and duty cycle correction. This multi-functional approach reduces the overall number of components needed in the frequency generation system, addressing the contradiction between meeting high frequency requirements and reducing circuit complexity.
2Speed
If frequency multiplication circuits are used to meet clock frequency requirements, then speed requirements are satisfied, but power consumption increases
Solution Approach 1:
The patent combines frequency doubling functionality with duty cycle correction into a single integrated circuit block. The frequency doubler receives a first clock signal and generates a second clock signal with twice the frequency, while simultaneously correcting duty cycle errors through embedded correction logic that adjusts the output duty cycle to be substantially 50%, eliminating the need for separate correction circuits.
3Device complexity
If duty cycle errors are not corrected in frequency doubled clock signals, then device complexity is reduced, but spurious behavior increases affecting ADC and PLL performance
Solution Approach 1:
The patent implements feedback-based duty cycle correction where the output duty cycle of the frequency doubler is monitored and adjusted. The correction mechanism uses feedback from the output signal to modify the duty cycle of the frequency doubled clock signal, ensuring it maintains a substantially 50% duty cycle and minimizing spurious behavior that would otherwise affect sensitive circuitry like ADCs and PLLs.
Solution Approach 2:
The patent introduces an intermediary duty cycle correction mechanism between the frequency doubling process and the output. This intermediary component adjusts the duty cycle of the frequency doubled clock signal without requiring complete redesign of the frequency multiplication architecture, thereby reducing spurious behavior while adding minimal complexity.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.