Frequency Doubler Calibration for 50% Duty Cycle Clocks
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Solution Overview
Problem
Designing frequency generation systems for portable RF devices that meet performance requirements for clock signals while balancing cost, board space, and power consumption is challenging, particularly due to issues with duty cycle errors in clock signals affecting sensitive circuitry like ADCs and PLLs.
Innovation Solution
An adjustable frequency doubling circuit that receives a first clock signal, generates a second clock signal with twice the frequency, and adjusts its duty cycle based on measurement to ensure a 50% duty cycle, thereby reducing spurious behavior and improving the performance of duty cycle-sensitive circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency doubling circuit is used to generate high frequency clock signals, then the clock frequency is doubled, but duty cycle errors are introduced that affect sensitive circuitry
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle of the doubled clock signal is measured and used to adjust the duty cycle of the input clock signal. The measurement circuit monitors the duty cycle parameter of the second clock signal, and the adjustment circuit modifies the first clock signal's duty cycle to compensate for errors introduced by the frequency doubling process, thereby maintaining accurate duty cycle at the output
Solution Approach 2:
The frequency doubling circuit performs self-calibration by using its own output signal to adjust its input signal. The measurement and adjustment circuits are integrated into the frequency doubling circuit itself, allowing it to automatically correct its own duty cycle errors without requiring external calibration equipment or manual adjustment
2Reliability
If multiple PLLs and DLLs are used to generate high frequency clocks, then clock performance requirements are met, but device complexity and cost increase
Solution Approach 1:
The patent makes a single frequency doubling circuit perform multiple functions: it doubles the clock frequency, corrects duty cycle errors through integrated measurement and adjustment circuits, and provides a calibrated clock signal to multiple downstream circuits. This eliminates the need for separate calibration circuits for each PLL or DLL, reducing overall system complexity while maintaining clock performance
Solution Approach 2:
The measurement circuit and adjustment circuit are merged into the frequency doubling circuit itself, creating an integrated solution. Rather than having separate calibration systems for each clock generation circuit, the patent combines frequency doubling, measurement, and adjustment functions into a single unified circuit block
3Ease of operation
If duty cycle errors are present in clock signals, then circuit operation continues, but spurious behavior increases in sensitive circuitry like ADCs and PLLs
Solution Approach 1:
The patent applies preliminary correction to the clock signal before it reaches sensitive circuitry. The measurement and adjustment circuits detect and correct duty cycle errors in advance, preventing spurious behavior from occurring in downstream circuits like ADCs and PLLs, rather than attempting to mitigate the effects after they manifest
Data Source
AI summary
In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.