Frequency Doubler Duty Cycle Correction for PLL Phase Noise
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Solution Overview
Problem
Locked loops in electronic devices, such as phase-locked loops (PLLs), face instability and accuracy issues due to duty cycle errors in reference signals, leading to phase noise and reference spurs in the output signals, which affect communication and synchronization operations.
Innovation Solution
A frequency doubler with duty cycle correction is employed, which selectively delays the rising or falling edge of the reference signal to balance even and odd periods, reducing duty cycle errors and sharing a phase detector to minimize deterministic errors, thereby improving the phase noise performance and reducing reference spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency doubler is used to increase the reference frequency to improve locked loop performance, then phase noise is reduced, but duty cycle errors cause even/odd period mismatch and reference spurs
Solution Approach 1:
The duty cycle correction circuit performs preliminary adjustment of the reference signal before it enters the frequency doubler. By correcting the duty cycle error in advance, the system prevents even/odd period mismatch and reference spurs from occurring in the frequency-doubled signal, while still benefiting from the phase noise reduction of frequency doubling
Solution Approach 2:
A duty cycle correction circuit is introduced as an intermediary component between the reference signal source and the frequency doubler. This intermediary circuit selectively delays rising or falling edges to balance the duty cycle, thereby eliminating the harmful effect of duty cycle errors while allowing the frequency doubler to function effectively
2Manufacturing precision
If duty cycle correction is applied to reduce reference spurs, then signal quality improves, but additional circuit complexity is introduced
Solution Approach 1:
Rather than correcting the entire signal waveform, the duty cycle correction circuit applies localized adjustment only to the problematic edges (rising or falling edges) of the reference signal. This selective edge delay approach achieves duty cycle balancing with minimal additional circuitry, avoiding the need for complex full-waveform correction mechanisms
Data Source
AI summary
An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.