Frequency Doubler Circuit With Duty Cycle Feedback for Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency doubling apparatuses using phase lock loop devices face challenges in minimizing jitter, requiring lower noise power sources or increased power dissipation, leading to higher costs and power consumption.
Innovation Solution
A frequency doubling apparatus comprising a frequency doubler circuit with a multiplexer, variable delay circuit, and divide-by-2 circuit, along with a duty cycle adjusting circuit that includes an average voltage generation circuit and comparison circuit, to generate and stabilize a frequency doubled clock signal with reduced jitter without increasing power dissipation or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase lock loop device is used for frequency doubling, then the clock signal frequency can be doubled accurately, but jitter increases and requires additional power or lower noise power sources
Solution Approach 1:
The frequency doubling function is segmented into distinct operational phases: a first phase where the multiplexer selects the first clock signal to generate the frequency doubled clock signal, and a second phase where it selects the second clock signal. This segmentation allows each phase to be optimized independently, reducing cumulative jitter while maintaining accurate frequency doubling.
Solution Approach 2:
The apparatus employs periodic switching between the first and second clock signals through the multiplexer, controlled by the selection signal generated from the divided frequency doubled clock signal. This periodic action creates a stable, repeating pattern that minimizes jitter accumulation while achieving consistent frequency doubling accuracy.
2Reliability
If lower noise power sources are used to reduce jitter in phase lock loop, then jitter decreases, but power dissipation increases and cost increases
Solution Approach 1:
The invention extracts the jitter-reduction function from the power supply system and implements it through the multiplexer-based clock signal selection mechanism. Instead of relying on lower noise power sources, the system achieves jitter reduction by selectively switching between two standard clock signals with opposite phases, using the inherent phase relationship to cancel jitter without requiring special power sources.
Solution Approach 2:
The system uses a second clock signal that is a phase-inverted copy of the first clock signal. By copying the clock signal with opposite phase and alternately selecting between the original and the copy, the system achieves jitter cancellation through differential operation, eliminating the need for expensive lower noise power sources.
3Reliability
If power dissipation is increased to reduce jitter in phase lock loop, then jitter decreases, but cost increases
Solution Approach 1:
The invention uses standard, inexpensive clock signals with finite duration cycles rather than requiring expensive, high-stability crystal oscillators or lower noise power sources. The multiplexer selectively uses these ordinary clock signals in a time-multiplexed manner, achieving jitter reduction through clever signal processing rather than expensive hardware.
Solution Approach 2:
The system changes the operational parameters of standard clock signals by alternately selecting between two phase-inverted signals through the multiplexer. This parameter change in the selection mechanism, rather than requiring changes in power supply quality, achieves jitter reduction at low cost using conventional components.
Data Source
AI summary
An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.