Frequency Doubler Feedback Loop for Duty-Cycle Stability
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Solution Overview
Problem
Modern electronic circuits face challenges in doubling high-frequency signals due to parasitic impedances in circuit components, leading to instability and inefficiency in clock signal processing.
Innovation Solution
A clock doubler circuit with a controllable delay and charge pump, operating in a negative feedback loop, generates a doubled frequency clock signal while correcting the duty cycle to 50% or other desired values, reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional frequency doubling circuits (PLL or DLL) are used to double high-frequency clock signals, then the output frequency is doubled, but parasitic impedances from circuit board traces, connectors, wires, and IC components cause instability and high power consumption
Solution Approach 1:
The patent introduces an on-chip controllable delay element as an intermediary component between the reference clock input and the frequency doubling output. This delay element, controlled by a feedback signal from a charge pump, allows the circuit to compensate for parasitic impedance effects by adjusting the phase and timing of the clock signal locally on the chip, thereby maintaining signal stability while achieving frequency doubling.
Solution Approach 2:
The patent implements a feedback mechanism using a charge pump that monitors the delayed clock signal and generates a feedback signal to control the controllable delay element. This closed-loop feedback system continuously adjusts the delay to compensate for variations caused by parasitic impedances, process variations, temperature changes, and voltage fluctuations, ensuring stable frequency doubling output.
2Speed
If conventional frequency doubling circuits are used, then frequency doubling is achieved, but the circuit occupies large chip area and consumes high power
Solution Approach 1:
The patent merges multiple functions into a single integrated on-chip circuit block: the controllable delay element, the charge pump, and the frequency doubling logic are combined into one compact unit. This integration eliminates the need for separate external components and interconnections, reducing both chip area and power consumption while maintaining the frequency doubling function.
Solution Approach 2:
The on-chip controllable delay element serves as a mediator that enables frequency doubling without requiring external high-frequency signal paths. By performing the delay and frequency multiplication locally on the chip, the circuit avoids power losses and area overhead associated with external traces, connectors, and bonding wires.
3Speed
If conventional frequency doubling circuits are used, then frequency doubling is achieved, but duty cycle distortion occurs and cannot be corrected
Solution Approach 1:
The charge pump in the patent provides feedback control that not only stabilizes the frequency but also corrects duty cycle distortion. By monitoring the delayed clock signal and adjusting the control signal to the controllable delay element, the feedback mechanism ensures that the output clock signal maintains the correct 50% duty cycle even under varying operating conditions.
Solution Approach 2:
The controllable delay element is dynamically adjusted by the feedback signal from the charge pump to compensate for duty cycle distortion. This dynamic control allows the circuit to adapt to process variations, temperature changes, and voltage fluctuations, maintaining precise duty cycle accuracy throughout operation.
Data Source
AI summary
An apparatus includes a controllable delay circuit, a clock doubler circuit, a low-pass filter, and a comparator. The controllable delay circuit generates a delayed clock signal from a reference clock signal. The clock doubler circuit generates an output clock signal from the delayed clock signal. A frequency of the output clock signal is twice a frequency of the reference clock signal. The low-pass filter receives the output clock signal and generates a filtered signal. The comparator generates an output signal by comparing the filtered signal with a reference signal.