Frequency Doubler Pulse Limiter for Narrow Pulse Propagation
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Solution Overview
Problem
At higher frequencies, such as those used in Wi-Fi devices operating at 7.2 GHz, the narrow pulse widths produced by frequency doublers in digital polar transmitters become challenging to propagate through wireless communication systems, leading to issues with signal processing and increased hardware complexity, power consumption, and crosstalk.
Innovation Solution
The implementation of a frequency doubler with a built-in pulse limiter that self-aligns and modifies narrow pulses to ensure they meet a minimum width threshold, eliminating the need for external control and reducing jitter and phase noise, thereby ensuring proper signal propagation without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency doubling is used to achieve higher operating frequencies (7.2 GHz and beyond), then the data throughput and communication speed are improved, but the pulse width becomes excessively narrow making signal propagation challenging
Solution Approach 1:
The patent applies preliminary action by extending the pulse width before it becomes too narrow to propagate effectively. The pulse extension circuit proactively widens pulses that fall below the threshold width, preventing propagation issues before they occur. This is achieved by detecting narrow pulses and extending their duration to meet minimum propagation requirements.
Solution Approach 2:
The patent changes the pulse width parameter dynamically based on the detected pulse characteristics. When a pulse is detected to be below the minimum width threshold, the circuit modifies its duration parameter to extend it to the required minimum width, thereby maintaining signal integrity at high frequencies.
2Reliability
If external control circuits are added to manage pulse widths, then pulse propagation reliability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent merges the pulse extension functionality directly into the frequency doubler circuit itself, eliminating the need for separate external control circuits. The frequency doubler is modified to include internal pulse width control mechanisms, combining multiple functions into a single integrated circuit that reduces overall system complexity.
Solution Approach 2:
The frequency doubler circuit performs self-service by automatically detecting and correcting its own pulse width issues. The circuit monitors its own output pulses and applies extension only when necessary, without requiring external control or intervention, thereby maintaining reliability while minimizing added complexity.
3Speed
If faster transitioning is used to handle narrow pulses, then signal processing speed is improved, but crosstalk and supply bouncing increase
Solution Approach 1:
The patent applies preliminary action by extending pulse widths before they become too narrow, which prevents the need for extremely fast transitioning that would cause crosstalk. By proactively maintaining minimum pulse widths, the circuit avoids the harmful effects of rapid switching while still processing signals efficiently.
Data Source
AI summary
This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.