Frequency Generator Delay Circuit for Fast Random Jitter
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Solution Overview
Problem
Existing frequency generators cannot produce a clock signal with fast and random jittering, as they are limited to regular and slow jittering methods.
Innovation Solution
A frequency generator with a capacitor, comparing unit, charging/discharging unit, delaying unit, and charging/discharging switch unit is designed to postpone the logic transition points of the clock signal, allowing for fast and random jittering by using a delaying unit to generate delayed charging/discharging signals that control the charging and discharging of the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the current flows of the first current source I1 and the second current source I2 are jittered, then frequency jitter can be achieved, but only regular and slow jittering can be realized
Solution Approach 1:
A delaying unit is introduced as an intermediary component between the comparing unit and the charging/discharging switch unit. This delaying unit receives the charging/discharging control signal and outputs a delayed version of the signal, thereby mediating the timing relationship and enabling fast and random jittering of the clock signal frequency without directly jittering the current sources
Solution Approach 2:
The patent replaces the traditional method of achieving frequency jitter by physically jittering current flows with a signal processing approach. Instead of mechanically or electrically jittering the current sources I1 and I2, the invention uses a delaying unit to introduce timing variations in the control signal, substituting a signal timing mechanism for a current modulation mechanism
2Manufacturing precision
If the voltage levels of the first reference voltage V1 and the second reference voltage V2 are jittered, then frequency jitter can be achieved, but only regular and slow jittering can be realized
Solution Approach 1:
The delaying unit serves as an intermediary that processes the charging/discharging control signal from the comparing unit. By introducing a variable delay time based on the delay signal, it enables fast and random frequency jittering of the clock signal without requiring direct jittering of the reference voltage levels
Solution Approach 2:
The delaying unit receives the charging/discharging control signal in advance and prepares a delayed version of the signal before it reaches the charging/discharging switch unit. This preliminary processing of the control signal allows the system to achieve fast frequency jittering by pre-computing the timing variations rather than reacting to them in real-time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively generates a clock signal with fast and random jittering capabilities, enabling the frequency generator to produce programmable jitter signals suitable for various applications.
Implementation Method 1
The first comparator COM1 has an inverted end receiving a first reference voltage V1 and an non-inverted end coupled to the capacitor C for comparing a voltage signal from the capacitor C and the first reference voltage V1. The second comparator COM2 has an non-inverted end receiving a second reference voltage V2 and an inverted end coupled to the capacitor C for comparing a voltage signal from the capacitor C and the second reference voltage V2.
Implementation Method 2
the frequency generator has a first current source I1 and a second current source I2 utilized for charging and discharging a capacitor C through a first switch SW1 and a second switch SW2 respectively
Data Source
AI summary
A frequency generator with frequency jitter is disclosed. The frequency generator comprises a capacitor, a comparing unit, a charging and discharging unit, a delay unit, and a charging and discharging switch unit. The comparing unit is coupled to the capacitor and generates a charging and discharging control signal according to a voltage of the capacitor. The charging and discharging unit is coupled to the capacitor. The delay unit is coupled to the comparing unit and receives a delay signal. The delay unit delays the charging and discharging control signal according to the delay signal to generate a charging and discharging delay signal. The charging and discharging switch unit is coupled to the charging and discharging unit and the delay unit, and charges or discharges the capacitor according to the charging and discharging delay signal.