Frequency-Halving Latch Buffer for Deterministic Cross-Clock Data Forwarding
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Solution Overview
Problem
Existing cross-clock domain data processing methods in field bus networks face challenges with resource utilization, stability, and buffer capacity, particularly in deterministic data forwarding scenarios where traditional methods like asynchronous FIFO and handshake mechanisms are inefficient due to complex logic and high resource usage.
Innovation Solution
A frequency-halving latch circuit with a data buffer having two units, a frequency-halving enable latch signal generation module, and a shift register to synchronize data across clock domains, reducing the need for additional counters and complex logic, thereby improving resource utilization and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFO method is used for cross-clock domain data processing, then data transmission between different clock domains is achieved, but the logic of empty and full signals becomes complicated and control of some signals becomes difficult to be accurate
Solution Approach 1:
The patent divides the cross-clock domain data transmission into two independent phases: write phase controlled by write enable signal and read phase controlled by read enable signal. Each phase has dedicated control logic that operates independently, avoiding the complex interdependent control logic of traditional asynchronous FIFO methods. The buffer is segmented into multiple storage units that can be independently controlled.
Solution Approach 2:
The patent introduces enable signals as intermediary control elements that mediate between the write clock domain and read clock domain. These enable signals act as intermediaries that coordinate data flow without requiring complex handshaking protocols, simplifying the control logic while ensuring accurate data transmission across clock domains.
2Reliability
If handshake mechanism method is used for cross-clock domain data processing, then data transmission accuracy is improved, but the delay of transmission becomes relatively high
Solution Approach 1:
The patent prepares enable signals in advance for both write and read operations. The write enable signal is generated based on write clock timing, and the read enable signal is generated based on read clock timing, both independently and in advance. This eliminates the need for real-time handshaking during data transmission, significantly reducing transmission delay while maintaining accuracy.
Solution Approach 2:
The patent enables continuous data transmission by maintaining independent write and read operations that do not block each other. The write operation continues uninterrupted by the read operation, and vice versa, as long as the respective enable signals are active. This continuous operation eliminates the idle waiting periods inherent in handshake mechanisms.
3Stability of the object's composition
If tight coupling method is used for cross-clock domain data processing, then data transmission stability is improved, but at least 3 memory cells are used so the resource utilization rate is relatively low
Solution Approach 1:
The patent segments the buffer into multiple storage units (first buffer unit, second buffer unit, etc.) that can be independently controlled by different enable signals. This segmentation allows the system to achieve stable cross-clock domain transmission using only 2 memory cells, one for each clock domain phase, eliminating the need for 3 or more memory cells required by tight coupling methods.
Solution Approach 2:
The patent changes the control parameter from requiring 3 memory cells to requiring only 2 memory cells by using enable signals as the primary control mechanism. The enable signals control which buffer unit is active for writing or reading, replacing the need for additional memory cells that would be required in traditional tight coupling implementations.
4Reliability
If traditional cross-clock domain processing circuit is introduced, then cross-domain clock problem is solved, but additional buffer units are required to store part of data which reduces resource utilization rate
Solution Approach 1:
The patent makes the existing buffer units serve dual purposes: they store data during cross-clock domain transmission and also provide buffering capacity for deterministic data forwarding. The same buffer units that solve the cross-clock domain problem are also used for data buffering, eliminating the need for separate additional buffer units and improving resource utilization rate.
Solution Approach 2:
The patent merges the cross-clock domain processing function with the data buffering function into a single integrated system. The buffer units simultaneously perform cross-domain data transmission and deterministic forwarding buffering, combining multiple functions into one resource-efficient structure that reduces the total number of buffer units required.
Data Source
AI summary
The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.