Frequency Interleaver Address Generation Using XOR Bit Streams
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Solution Overview
Problem
In interleave processes, such as frequency interleave, the production of valid addresses is unreliable, leading to issues in data writing and reading, which affects the integrity of data rearrangement during transmission.
Innovation Solution
The implementation of a data processing apparatus and method that utilizes a modified address production expression, specifically incorporating exclusive OR operations and pseudo-random number generators, ensures the production of valid addresses by adjusting the bit streams for write and read addresses, ensuring they fall within the data length, thereby enhancing address reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address production methods are used in frequency interleave, then the interleave process can be implemented, but valid addresses cannot be reliably produced leading to data integrity issues
Solution Approach 1:
The patent modifies the address production expression by changing the mathematical operation from addition to exclusive OR (XOR) between the pseudo-random number and the base address. This parameter change in the address calculation formula ensures that valid addresses are always produced while maintaining system reliability without significantly increasing complexity.
Solution Approach 2:
The patent incorporates a validation mechanism that checks whether produced addresses fall within the valid data range. When invalid addresses are detected, the system provides feedback to adjust the address production process, ensuring continuous generation of valid addresses for memory access operations.
2Productivity
If address production is performed without validation, then the processing speed is maintained, but invalid addresses are generated causing data rearrangement failures
Solution Approach 1:
The patent performs preliminary validation checks during the address production phase itself, rather than after address generation. By incorporating validation logic into the address calculation expression using XOR operations, the system ensures addresses are valid before they are used for memory operations, preventing processing delays while maintaining reliability.
3Device complexity
If a simple address generation method is used, then the hardware implementation is simplified, but continuous invalid address production cannot be prevented
Solution Approach 1:
The patent changes the mathematical operation in the address production expression from addition to exclusive OR (XOR). This simple parameter change in the formula ensures that the least significant bit of the pseudo-random number directly controls address validity, guaranteeing continuous production of valid addresses without complex validation circuits.
Data Source
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AI summary
The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave. In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.