Frequency-Locked Clock Generator With Frequency-to-Current Feedback
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) suffer from poor jitter and updating performance when generating high frequency clock signals from low frequency input signals, especially for large divider ratios, due to limited loop bandwidth and high costs associated with expensive crystal oscillators.
Innovation Solution
A frequency-locked clock generator is developed, utilizing a voltage-controlled oscillator (VCO), frequency-to-current converter, reference current source, and gain stage, which adjusts the output signal's frequency based on a difference between converter current and reference current, eliminating the need for a reference clock and allowing for improved jitter and updating performance by locking the frequency to a time constant determined by the converter and reference current source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a phase-locked loop (PLL) is used to generate a high frequency output clock signal from a low frequency input signal, then the output frequency can be controlled, but the loop bandwidth is limited and jitter performance suffers for large divider ratios
Solution Approach 1:
The patent changes the fundamental operating parameters of the frequency control system by replacing phase detection with frequency-to-current conversion. This allows the loop bandwidth to be determined by the RC time constant rather than being limited by the reference frequency, enabling adequate updating performance for large divider ratios while maintaining jitter control through the feedback mechanism that forces converter current to equal reference current
2Reliability
If a crystal oscillator is used to generate the reference input signal, then frequency stability can be achieved, but the cost increases significantly
Solution Approach 1:
The patent replaces the expensive crystal oscillator with a low-cost RC-based reference current source. The frequency stability previously provided by the crystal oscillator is achieved through the feedback mechanism that locks the VCO frequency to the RC time constant, eliminating the need for expensive frequency-determining components while maintaining adequate stability for the application
Solution Approach 2:
The system uses the VCO's own output signal (through frequency division and frequency-to-current conversion) to generate the feedback that controls its frequency. This self-service mechanism eliminates the need for an external reference oscillator, reducing cost while maintaining frequency control through the automatic frequency locking to the RC time constant
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a reduced-cost, accurate, and stable output signal with enhanced jitter and updating performance for large divider ratios, eliminating the need for expensive crystal oscillators and allowing for larger loop bandwidth, ensuring adequate VCO updating and reduced jitter.
Implementation Method 1
A voltage-controlled oscillator (VCO) generates an output signal having a frequency that is adjustable
Implementation Method 2
A frequency-to-current converter generates a converter current proportional to a frequency of the feedback signal
Implementation Method 3
A gain stage generates a control signal having a value that is based on a difference between the converter current and a reference current
Implementation Method 4
Overall, the feedback of the frequency-locked clock generator forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current
Data Source
AI summary
A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.