Frequency Multiplier Circuit for Half-Frequency Tester Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed integrated circuits (ICs) are challenging to test due to their operating speeds exceeding those of conventional testing devices, necessitating the use of complex and costly on-chip phase-locked loop (PLL) circuits to overcome testing device limitations.
Innovation Solution
An integrated circuit with a double frequency clock generator and test data generator circuit that operates in both standard and high-speed modes, utilizing phase-shifted clock signals to effectively test semiconductor devices at full frequency using a half frequency tester, thereby doubling the frequency of clock and test data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional half frequency tester is used to test high-speed ICs, then the testing device can operate at lower frequencies, but the testing device cannot accurately test high-speed devices operating at frequencies higher than its capability
Solution Approach 1:
The patent divides the testing system into two independent parts: a simple half-frequency tester and a frequency multiplier circuit. The frequency multiplier circuit is segmented into a clock generator that generates doubled-frequency clock signals and a data generator that generates test data at the doubled frequency. This segmentation allows the tester to remain simple while the frequency multiplier handles the high-speed requirement.
Solution Approach 2:
The frequency multiplier circuit acts as an intermediary between the half-frequency tester and the high-speed device under test. It receives test signals at half frequency from the tester and outputs signals at double frequency to the device, enabling the tester to indirectly test high-speed devices without requiring the tester itself to operate at high frequencies.
2Speed
If an on-chip phase-locked loop (PLL) circuit is fabricated to overcome testing device limitations, then the testing device can test high-speed ICs, but the fabrication process becomes more complex and costly
Solution Approach 1:
The patent extracts the frequency multiplication function from a complex on-chip PLL circuit and implements it using simpler external components. Instead of fabricating a complete PLL circuit on the IC, the invention uses a separate frequency multiplier circuit that can be implemented with basic logic gates and registers, significantly simplifying the fabrication process.
Solution Approach 2:
The invention replaces the expensive and complex on-chip PLL circuit with a simpler, more economical frequency multiplier implementation using standard logic gates (XOR, XNOR) and registers. This approach uses cheaper components to achieve the same functional goal of frequency multiplication for testing purposes.
3Reliability
If the testing device operates at the same frequency as the high-speed IC, then accurate testing can be performed, but the testing device must be designed and fabricated to match the high-speed requirements
Solution Approach 1:
The patent introduces dynamic frequency multiplication where the frequency multiplier circuit can operate in different modes (1x and 2x) depending on the testing requirements. The clock generator dynamically generates clock signals at the appropriate frequency, and the data generator dynamically adjusts test data generation based on the selected mode, enabling flexible testing of devices at different speeds.
Data Source
AI summary
An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1× mode) and high-speed rate (2× mode) to a device under test. In 1× mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2× mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.