Programmable Frequency Multiplier for Stable DVFS Clock Transitions
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Solution Overview
Problem
Abrupt changes in clock frequency during dynamic voltage and frequency scaling (DVFS) can cause undesirable disruptions, leading to timing failures and system instability due to supply voltage perturbations.
Innovation Solution
A frequency multiplier circuit with a programmable transition controller, pre-multiplier controller, phase alignment controller, and frequency generator override controller, which control the transitioning frequency relationship between signal frequencies to minimize perturbations and improve settling time by employing linear ramp transitions and phase alignment mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased quickly to improve performance, then the system performance increases, but the supply voltage undershoots causing timing failures
Solution Approach 1:
The frequency multiplier circuit performs preliminary actions by pre-charging capacitive loads and gradually ramping up the frequency before full operation is required. This prepares the system in advance to handle the increased frequency transition smoothly, preventing voltage undershoot and timing failures while achieving high performance.
2Use of energy by moving object
If the clock frequency is decreased quickly to conserve power, then the power consumption decreases, but the supply voltage overshoots causing system instability
Solution Approach 1:
Before decreasing the frequency to conserve power, the circuit performs preliminary discharge of capacitive loads through controlled ramps. This preliminary action prevents sudden current decreases that would cause voltage overshoot, maintaining system stability while achieving power savings.
3Loss of time
If abrupt frequency changes are made to improve response time, then the response time improves, but device perturbations increase causing system unusability
Solution Approach 1:
The frequency multiplier circuit implements dynamic frequency adjustment with programmable transition rates. Instead of fixed abrupt changes, the circuit adapts the frequency transition speed based on system conditions, achieving fast response when needed while minimizing perturbations through controlled dynamic transitions.
Solution Approach 2:
The circuit changes the transition parameters (frequency ramp rate, hold times) dynamically based on system state. By adjusting these parameters, the system achieves fast response times when conditions permit while reducing device perturbations when conditions require more conservative transitions.
Data Source
AI summary
A frequency multiplier circuit includes a first multiplier circuit to generate a first digital value representing a received reference signal having a reference frequency and reference phase, the multiplier circuit to multiply the first digital value by a multiplier value. Comparison circuitry compares the first digital value to an output digital value representing an output signal having an output frequency and an output phase, the comparison circuitry to generate an error signal based on the comparison. A programmable loop filter generates a control signal based at least in part on the error signal. A frequency generation circuit produces the output signal having the output frequency and phase. A phase-to-digital converter generates and feeds the output digital value to the phase comparison circuitry. A programmable transition controller controls a transitioning frequency relationship between a first signal frequency of a first locked output signal and a desired second signal frequency.