Frequency Multiplier Pulse Overlap Correction for Higher Clock Rates
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Solution Overview
Problem
Conventional frequency multipliers using delay locked loops face increased power consumption and reduced maximum frequency due to overlap between pulses generated by process voltage temperature variations, leading to unnecessary operation of PMOS and NMOS transistors.
Innovation Solution
A frequency multiplier design that includes a pulse generator with an intermediate pulse signal generation unit and an overlap correction unit, utilizing NOR and NAND logic gates to correct overlaps between intermediate pulse signals, thereby reducing power consumption and increasing the maximum frequency generated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pulse generation is performed without overlap correction in a frequency multiplier, then the circuit structure is simpler, but power consumption increases due to unnecessary transistor operation caused by pulse overlap
Solution Approach 1:
The overlap correction unit performs preliminary detection and correction of pulse overlaps before the transistors are activated. By anticipating and preventing the overlap condition in advance, the system avoids the harmful effect of simultaneous PMOS and NMOS conduction, thereby reducing power consumption without requiring complex real-time control mechanisms.
Solution Approach 2:
The overlap correction unit acts as an intermediary component between the pulse generation unit and the transistor stage. It receives intermediate pulse signals, detects overlaps, generates correction signals, and feeds them back to prevent harmful transistor operation. This mediator approach allows the system to maintain simple transistor design while eliminating power waste through intelligent signal conditioning.
2Speed
If multiplication rate is increased in a frequency multiplier, then the output frequency is higher, but the maximum frequency that can be generated is reduced due to increased junction capacitance
Solution Approach 1:
The invention extracts and removes the harmful element (pulse overlap) from the system. By separating the overlap detection and correction functions into a dedicated unit, the system eliminates the source of excessive capacitance loading on the transistor output. This allows higher multiplication rates to be achieved without the penalty of increased junction capacitance that would otherwise limit the maximum operable frequency.
3Use of energy by moving object
If overlap correction is implemented in a frequency multiplier, then power consumption is reduced, but the device complexity increases due to additional correction circuits
Solution Approach 1:
The overlap correction unit is merged with the existing pulse generation unit to form an integrated frequency multiplier system. The correction functionality is combined with the intermediate pulse signal generation stage, allowing overlap detection and correction to be performed within the existing signal path. This integration minimizes the additional circuitry required while achieving significant power consumption reduction.
4Speed
If multiplication rate is increased in a frequency multiplier, then the output frequency is higher, but power consumption increases due to increased number of transistors and junction capacitance
Solution Approach 1:
The invention converts the potentially harmful effect of high multiplication rates (increased capacitance and power consumption) into a benefit by implementing overlap correction. The correction unit identifies and eliminates the specific condition (pulse overlap) that causes excessive transistor operation and power waste. This allows the system to operate at high multiplication rates efficiently, transforming what would be a disadvantage into an opportunity for optimized performance.
Data Source
AI summary
A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.