Frequency Multiplier Duty-Cycle Calibration for Spur Suppression
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Solution Overview
Problem
The quality of output signals in clock frequency multiplier circuits is compromised by an alternating duty cycle of the input reference clock signal, leading to spurious signals in radio frequency communications systems, as the duty cycle is not always 50%.
Innovation Solution
A digital phase-locked loop circuit with a clock controller, clock calibration circuit, and clock frequency multiplier that receives an output signal from a time-to-digital converter to determine and calibrate the duty cycle error of the reference clock signal, generating a control signal to adjust the duty cycle to 50%, thereby reducing spurious signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the duty cycle of the reference clock signal is not 50%, then the frequency multiplication can be performed, but spurious signals occur in the output signal
Solution Approach 1:
The patent applies preliminary action by calibrating the duty cycle of the reference clock signal before frequency multiplication. The clock calibration circuit pre-adjusts the duty cycle to 50% using a control signal generated from duty cycle error detection, ensuring that the reference clock signal is properly conditioned before it enters the frequency multiplier, thereby preventing spurious signal generation
Solution Approach 2:
The patent implements feedback by detecting the duty cycle of the reference clock signal, comparing it against the ideal 50% duty cycle, and generating a control signal based on the detected error. This feedback mechanism continuously monitors and adjusts the duty cycle to maintain optimal performance and eliminate spurious signals
2Measurement precision
If a frequency multiplier circuit is used to multiply the reference clock frequency, then the phase noise performance improves, but the output signal quality deteriorates due to alternating duty cycle
Solution Approach 1:
The clock calibration circuit performs preliminary calibration of the reference clock signal's duty cycle before it enters the frequency multiplier. By pre-adjusting the duty cycle to 50%, the system ensures high-quality output signals while maintaining the frequency multiplication function that improves phase noise performance
Solution Approach 2:
The patent changes the duty cycle parameter of the reference clock signal from its original value to the optimal 50% value through calibration. This parameter adjustment resolves the contradiction by ensuring the reference clock has the correct duty cycle characteristics, allowing the frequency multiplier to produce high-quality output signals without spurious components
Data Source
AI summary
A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method, where the frequency multiplier includes a clock controller configured to: receive an output signal from a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal, a clock calibration circuit configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal, and a clock frequency multiplier configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.