Frequency-Multiplying DDS with Low-Clock Accumulator Architecture
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Solution Overview
Problem
Direct digital synthesizers (DDS) face limitations in achieving high output frequencies, particularly above 10 GHz, due to constraints on the reference clock frequency and processing delay, making them unsuitable for high-frequency radar and microwave communications applications.
Innovation Solution
A frequency-multiplying DDS is introduced, which includes a digital multiplier, phase accumulator, and post-accumulator digital processing section, allowing the accumulator to operate at a lower reference clock frequency while producing a higher output frequency by multiplying the digital tuning word and rotating digital waveforms, enabling synthesis of frequencies up to 10 GHz and beyond.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the reference clock frequency is increased to achieve higher output frequencies, then the maximum output frequency is improved, but the processing delay and system complexity increase
Solution Approach 1:
The patent divides the frequency multiplication process into two independent stages: (1) a low-speed accumulator operating at fREF/B that generates coarse frequency multiplication through digital tuning word multiplication, and (2) a high-speed post-accumulator operating at fREF that performs fine frequency adjustment and waveform synthesis. This segmentation allows the system to achieve high output frequencies without requiring the main accumulator to operate at high speeds, thereby reducing processing delay while maintaining frequency accuracy.
2Speed
If the reference clock frequency is increased to achieve higher output frequencies, then the maximum output frequency is improved, but the device complexity increases
Solution Approach 1:
The patent segments the DDS system into distinct functional blocks with clearly defined operating frequencies: a low-speed accumulator stage for frequency multiplication, a high-speed post-accumulator stage for waveform synthesis, and a serializer for output. This modular segmentation reduces system complexity by allowing each block to be optimized independently for its specific operating frequency, avoiding the need for the entire system to operate at high speeds.
Solution Approach 2:
The patent introduces an intermediary frequency multiplication stage using digital tuning word multiplication by a factor B. This intermediary process converts a low reference clock frequency into an equivalent high-frequency output, acting as a mediator that bridges the gap between low-speed accumulation and high-frequency synthesis requirements, thereby reducing overall system complexity.
3Productivity
If the accumulator operates at lower frequency, then the processing load is reduced, but the output frequency capability is limited
Solution Approach 1:
The patent employs periodic frequency multiplication where the accumulator increments by a multiplied tuning word value (M×B) at low speed, effectively simulating B times the reference clock frequency. This periodic multiplication approach allows the low-speed accumulator to generate frequency components equivalent to a high-speed system, maintaining output frequency capability while reducing processing load.
Solution Approach 2:
The patent replaces the traditional mechanical approach of operating the accumulator at high clock frequencies with a digital signal processing approach using frequency multiplication algorithms. By substituting the high-speed clocking mechanism with mathematical multiplication operations, the system achieves equivalent high-frequency output with reduced processing load on the accumulator.
Data Source
AI summary
A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.