Frequency-Multiplying DDS for High-Frequency Output at Lower Clock Speed
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Solution Overview
Problem
Direct digital synthesizers (DDS) face limitations in achieving high output frequencies, particularly above 10 GHz, due to constraints on the reference clock frequency and processing delay, making them unsuitable for high-frequency radar and microwave communications applications.
Innovation Solution
A frequency-multiplying DDS is introduced, which includes a digital multiplier, phase accumulator, and post-accumulator digital processing section, allowing the accumulator to operate at a lower reference clock frequency while producing output frequencies up to eight times higher by multiplying the digital tuning word and rotating digital waveforms, enabling synthesis of high-frequency waveforms suitable for radar and microwave communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the reference clock frequency is increased to achieve higher output frequencies, then the maximum output frequency capability is improved, but the processing delay and system complexity increase
Solution Approach 1:
The patent divides the high-frequency synthesis task into multiple lower-frequency accumulator operations. Instead of using a single high-speed accumulator, the system uses multiple accumulators operating at lower clock frequencies, each handling a portion of the frequency multiplication task. This segmentation reduces the processing delay of individual accumulators while achieving the same overall output frequency capability.
Solution Approach 2:
The patent introduces an intermediary frequency multiplication stage between the accumulator and the output. The accumulator operates at a manageable reference clock frequency, and its output is then frequency-multiplied to achieve the desired high output frequency. This intermediary approach allows the accumulator to run at lower speeds without limiting the final output frequency capability.
2Device complexity
If the reference clock frequency is limited to reduce processing delay, then the device complexity is reduced, but the maximum output frequency capability deteriorates
Solution Approach 1:
The patent changes the operational parameters of the frequency synthesis system by decoupling the accumulator clock frequency from the output frequency. The accumulator operates at a lower reference clock frequency with manageable processing delay, while frequency multiplication techniques are applied to achieve higher output frequencies. This parameter change allows the system to maintain low complexity while achieving high output frequency capability.
3Measurement precision
If the accumulator operates at high reference clock frequency to achieve high output frequencies, then the frequency tuning resolution is improved, but the processing demands and system complexity increase
Solution Approach 1:
The patent segments the frequency synthesis function across multiple accumulators operating in parallel or sequence at lower clock frequencies. Each accumulator maintains the necessary frequency tuning resolution through its tuning word, and the combined output achieves the desired high frequency. This segmentation reduces the processing demands on individual accumulators while preserving frequency tuning resolution.
Data Source
AI summary
A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.