Frequency Offset Calibration via Intermittent Clock Estimation

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Solution Overview

Problem

Conventional communication devices face challenges in calibrating frequency offset during sleep mode, leading to poor page indication channel reception performance, especially with longer DRX cycles or large frequency offsets, requiring additional complexity and hardware.

Innovation Solution

The communication device is periodically awakened during a DRX cycle to estimate and calibrate the accumulated timing offset of the clock signal, allowing for efficient frequency offset calibration with simple implementation and low hardware cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the communication device is awakened at the end of each DRX cycle to estimate accumulated timing offset, then the frequency offset can be calibrated, but when a longer DRX cycle is used or the frequency offset is too large, the accumulated frequency offset exceeds the estimation capability, resulting in low PICH reception performance

Engineering Contradiction:
Improvefrequency offset estimation accuracyVSAvoidDRX cycle length
Core Design Contradiction:
Measurement precisionVSDuration of action of moving object

Solution Approach 1:

The patent applies preliminary action by dividing the DRX cycle into multiple phases and performing frequency offset estimation at intermediate points rather than waiting until the end. The communication device wakes up at a first time point to receive PICH messages and performs initial frequency offset estimation, then wakes up again at a second time point to perform additional estimation and calibration. This preliminary intermediate measurement prevents the accumulated frequency offset from exceeding estimation capabilities.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the single end-of-cycle calibration into multiple calibration stages distributed throughout the DRX cycle. By dividing the calibration process into multiple smaller estimation tasks performed at different time points, each estimation operates within acceptable accuracy ranges while collectively achieving comprehensive frequency offset calibration across the entire cycle.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If a high accuracy clock signal is used to calibrate the clock signal of 32 KHz, then the frequency offset can be calibrated accurately, but an additional calibrating mechanism is required, resulting in higher system complexity

Engineering Contradiction:
Improvefrequency offset calibration accuracyVSAvoidcalibrating mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies self-service by having the communication device use its own received PICH messages as the reference signal for frequency offset estimation, rather than requiring an external high-accuracy clock signal. The device extracts timing information from the received paging messages itself, performing autonomous calibration without additional external calibration mechanisms or hardware.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses the PICH message as an intermediary carrier that contains timing reference information. Instead of directly using a high-accuracy external clock signal, the received PICH message serves as an intermediary reference that the device can use to estimate and correct its own frequency offset, simplifying the calibration mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9307571B2Communication device and frequency offset calibrating method
Publication Date: 2016.04.05 MEDIATEK SINGAPORE PTE LTD
  • US9307571B2 patent drawing
  • US9307571B2 patent drawing
  • US9307571B2 patent drawing

AI summary

A frequency offset calibrating method for use in a communication device connected to a communication system is provided. The method includes the following steps: determining a discontinuous reception cycle; awakening the communication device to a working mode from a sleep mode every discontinuous reception cycle and keep the communication device in the working mode for a first time period to receive a paging indication channel message from a communication network periodically; and awakening the communication device at a second time period other than the first time period during a first discontinuous reception cycle, thereby estimating an accumulated timing offset of a clock signal of the communication device and calibrating a frequency offset of the clock signal. In the invention, the accumulated timing offset of the clock signal can be calibrated efficiently to increase the reception performance of the page indication channel message with simple implementation and low hardware cost.