Frequency Offset Compensation Circuit for QPSK Demodulation
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Solution Overview
Problem
Existing frequency shift compensation circuits for QPSK demodulation are complex, not suitable for high frequencies, and have high electrical consumption, making them inefficient for applications like the V-band where frequency accuracy is critical.
Innovation Solution
A frequency offset compensation device comprising a first circuit to generate phase-shifted signals, a second circuit to determine bit states from these signals, and a third circuit to adjust a gain value, allowing for accurate demodulation even with significant frequency offsets up to 1000ppm, using a combination of phase rotation and digital filtering to compensate for frequency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a crystal is used to generate the FLO frequency, then the frequency accuracy is improved, but the cost and device complexity increase
Solution Approach 1:
The patent replaces the expensive crystal oscillator with a digitally controlled oscillator (DCO) that uses software/firmware control for frequency adjustment. This digital approach uses simpler, cheaper components while achieving the required frequency accuracy through algorithmic compensation rather than hardware precision.
Solution Approach 2:
The patent substitutes the mechanical crystal oscillator with a digital control system that uses phase detectors, numerators, and digital filters to achieve frequency synchronization. This replaces a physical mechanical resonance system with an electronic-digital control architecture.
2Measurement precision
If a frequency offset compensation circuit is added, then the frequency accuracy is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent divides the frequency offset compensation function into separate modular blocks: a phase detector that measures the offset, a numerator that generates correction signals, and a digital filter that processes the correction. This segmentation allows each module to perform a specific function with simplified design.
Solution Approach 2:
The compensation circuit continuously monitors its own performance through the phase detector and automatically adjusts the DCO frequency using the feedback loop. The system self-corrects frequency offsets without external intervention, maintaining synchronization autonomously.
3Measurement precision
If a frequency offset compensation circuit is added, then the frequency accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic decrease of the gain in the digital filter during the first phase where known symbols are received. This periodic adjustment allows the system to achieve frequency synchronization efficiently during the initial phase, reducing the continuous power burden during normal operation.
Solution Approach 2:
The patent changes the gain parameter of the digital filter over time - high gain during initial synchronization when known symbols are available, and lower gain during normal operation. This dynamic parameter adjustment optimizes power consumption by reducing processing intensity once synchronization is achieved.
4Reliability
If the FLO frequency differs from the Fc frequency, then the demodulation errors increase, but using a crystal to ensure frequency match increases cost
Solution Approach 1:
The patent implements a feedback loop where the phase detector continuously monitors the frequency offset between FLO and Fc, and the DCO adjusts its frequency based on this feedback. This closed-loop control ensures demodulation accuracy by dynamically correcting frequency mismatches rather than relying on initial hardware precision.
Solution Approach 2:
The patent dynamically changes the DCO frequency parameter based on the detected offset, allowing the system to adapt to frequency mismatches. This parameter adjustment approach maintains demodulation reliability without requiring the DCO to be initially extremely precise.
Data Source
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Figure 2
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AI summary
This description relates to a device (2) comprising a first circuit (CORR) receiving first and second signals (I1(t), Q1(t)) and a third phase-shift signal (THETA), and generating fourth and fifth signals (I2(t), Q2(t)) by applying the phase shift to the first and second signals. The second circuit (CORR) determines, when the first and second signals correspond to a known QPSK symbol, a bit (UP/DW) from a sampling of the sum and difference of the fourth and fifth signals, provides a digital signal (IN-LOOP) corresponding to a multiplication of the bit (UP/DW) by a gain (G), and periodically decreases the gain (G) to a value of unity. The third circuit (LOOP) determines the third signal (THETA) from the digital signal (LOOP-IN).