Frequency Quintupling Circuit Using Five-Phase Charge Pumps

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Frequency quintupling circuits face issues with VCO pulling and frequency modulation due to noise in the power supply, which affect the accuracy of the output clock frequency.

Innovation Solution

A circuit comprising multiple tri-stage charge pumps and a load is used to process a five-phase clock, outputting a current that is summed to produce an output clock with a quintuple frequency, reducing VCO pulling and noise modulation by employing a five-phase clock structure and a load that provides impedance to convert the current into the output clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a phase lock loop with VCO is used for frequency quintupling, then frequency multiplication is achieved, but VCO pulling and frequency modulation due to power supply noise occur

Engineering Contradiction:
Improveoutput clock frequency accuracyVSAvoidVCO pulling and noise modulation
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the VCO component from the frequency quintupling system, replacing it with a direct current pumping approach using five-phase clocks and charge pumps. This eliminates the source of VCO pulling and noise modulation while maintaining frequency multiplication functionality through a different mechanism that doesn't rely on voltage-controlled oscillation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces current as an intermediary between the input clock signal and output frequency quintupled signal. Instead of using voltage control through a VCO, the system uses current pumping through five-phase clocks and charge pumps to achieve frequency multiplication, thereby avoiding the harmful effects associated with voltage-controlled oscillation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional frequency quintupling methods are used, then frequency multiplication is achieved, but the system is susceptible to interfering signals and power supply noise

Engineering Contradiction:
Improvefrequency stabilityVSAvoidinterfering signals and noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes the VCO from the system architecture, which is the component most susceptible to interfering signals and power supply noise. By replacing it with a current-based frequency multiplication approach using five-phase clocks and charge pumps, the system achieves frequency multiplication without the reliability issues associated with VCO susceptibility to external interference.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the voltage-controlled mechanical oscillation system (VCO) with an electrical current-based system. This replacement eliminates the mechanical-like oscillation that is susceptible to interference, using instead a more robust electrical current pumping mechanism that is less vulnerable to external noise and interfering signals.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10715038B1Apparatus and method for frequency quintupling
Publication Date: 2020.07.14 REALTEK SEMICON CORP
  • US10715038B1 patent drawing
  • US10715038B1 patent drawing
  • US10715038B1 patent drawing

AI summary

A circuit includes a first TSCP (tri-stage charge pump), a second TSCP, a third TSCP, a fourth TSCP, a fifth TSCP, and a load. The first TSCP receives a first phase and a third phase of a five-phase clock and outputs a first current to an output node. The second TSCP receives a second phase and a fourth phase of the five-phase clock and outputs a second current to the output node. The third TSCP receives a third phase and a fifth phase of the five-phase clock and outputs a third current to the output node. The fourth TSCP receives a fourth phase and the first phase of the five-phase clock and outputs a fourth current to the output node. The fifth TSCP receives a fifth phase and the second phase of the five-phase clock and outputs a fifth current to the output node. The load terminates the output node.