Frequency Scaled Message Scheduler Data Path Circuit
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Solution Overview
Problem
Current hashing operations in blockchain mining, particularly for Bitcoin, are computationally intensive and energy-consuming due to the need to find a nonce that produces a hash value below a specific target, leading to high energy costs and inefficiencies.
Innovation Solution
A hashing accelerator with a frequency scaled message scheduler data path circuit is introduced, which operates at a slower frequency than the message digest data path circuit to reduce energy consumption while maintaining overall hash throughput, and includes a fully-unrolled hash stage circuit with parallel scheduler circuits to compute multiple message elements per cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the message scheduler data path circuit operates at the same frequency as the message digest data path circuit, then the hash throughput is maximized, but the power consumption increases by 10%-15%
Solution Approach 1:
The patent applies dynamic frequency scaling to the message scheduler data path circuit, allowing it to operate at different frequencies depending on the operational phase. During the message scheduling phase, it operates at a reduced frequency (e.g., 200 MHz), while during the message digest phase, it synchronizes with the higher frequency of the message digest circuit. This dynamic adjustment resolves the contradiction by reducing power consumption during less critical operations while maintaining high throughput during critical hashing operations.
Solution Approach 2:
The patent changes the operational parameter (frequency) of the message scheduler data path circuit from a fixed high frequency to a variable frequency that can be scaled down during message scheduling operations. This parameter change allows the system to achieve 10%-15% power reduction during scheduling while maintaining overall hash throughput by recovering full frequency during the message digest phase.
2Use of energy by moving object
If the message scheduler data path circuit operates at a reduced frequency, then power consumption decreases by 10%-15%, but the hash throughput may be reduced
Solution Approach 1:
The patent segments the hashing operation into two distinct phases: message scheduling and message digest computation. The message scheduler circuit and message digest circuit operate semi-independently with different frequency requirements. By segmenting the operation, the system can reduce frequency (and power consumption) during the scheduling phase while maintaining high frequency during the computationally intensive digest phase, thus preserving overall hash throughput.
Solution Approach 2:
The patent implements periodic frequency switching where the message scheduler data path circuit alternates between reduced frequency during message scheduling intervals and full frequency during message digest intervals. This periodic action pattern allows the system to achieve net power savings while maintaining throughput by ensuring that high-frequency operation occurs during the critical path of the hashing algorithm.
3Productivity
If fully-unrolled hash stage circuits are used, then hash computation speed increases, but the silicon area increases
Solution Approach 1:
The patent applies dynamic unrolling where the hash stage circuit is fully unrolled (computationally expanded) only during the message digest phase when maximum computation speed is needed. During the message scheduling phase, the circuit operates in a more compact, less unrolled state. This dynamic unrolling strategy achieves high computation speed when needed while reducing silicon area utilization during other phases.
Solution Approach 2:
The patent implements periodic full unrolling of the hash stage circuit, activating the complete unrolled structure only during message digest computation intervals. Between these intervals, during message scheduling, the circuit uses a more compact representation. This periodic activation of full unrolling achieves high throughput during critical phases while reducing average silicon area requirements.
Data Source
AI summary
Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.